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| document no. e0251n20 (ver. 2.0) date published july 2002 (k) japan url: http:// www.elpida.com ? elpida memory,inc. 2002 elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. data sheet 288m bits direct rambus dram for high performance solution pd488588ff-c80-40 ( 512k words 18 bits 32s banks) description the direct rambus dram (direct rdram) is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. the pd488588ff is 288mbits direct rambus dram (rdram ? ), organized as 16m words by 18 bits. the use of rambus signaling level (rsl) technology permits 800mhz transfer rates while using conventional system and board design technologies. direct rdram devices are capable of sustained data transfers at 1.25ns per two bytes (10ns per sixteen bytes). the architecture of the direct rdrams allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. the separate control and data buses with independent row and column control yield over 95% bus efficiency. the direct rdrams four banks support up to four simultaneous transactions. system oriented features for mobile, graphics and large memory systems include power management, byte masking. the pd488588ff is offered in a csp horizontal package suitable for desktop as well as low-profile add-in card and mobile applications. direct rdrams operate from a 2.5v supply. features ? highest sustained bandwidth per dram device 1.6 gb/s sustained data transfer rate separate control and data buses for maximized efficiency separate row and column control buses for easy scheduling and highest performance 32 banks: four transactions can take place simultaneously at full bandwidth data rates ? low latency features write buffer to reduce read latency 3 precharge mechanisms for controller flexibility interleaved transactions ? advanced power management: multiple low power states allows flexibility in power consumption versus time to active state power-down self-refresh ? overdrive current mode ? organization: 2k bytes pages and 32 banks, x 18 ? uses rambus signaling level (rsl) for up to 800mhz operation ? package : 80-ball fbga ( bga ? ) (17.16 10.2) application the pd488588ff is most appropriate for the applications, such as consumer products demanding vivid animations, processor memory for multimedia and 3d graphics, network processing and storage systems requiring scalability to accommodate future designs.
data sheet e0251n20 (ver. 2.0) 2 pd488588ff-c80-40 ordering information part number organization* words bits internal banks clock frequency mhz (max.) /ras access time (ns) package PD488588FF-C80-40-DH1 512k x 18 x 32s 800 40 80-ball fbga ( bga) (17.16 10.2) note: the 32s designation indicates that this rdram core is composed of 32 banks which use a split bank architecture data sheet e0251n20 (ver. 2.0) 3 pd488588ff-c80-40 pin configuration 80-ball fbga ( bga) (17.16 10.2) top view 10 o o o o 9 8 o o o o o o o o o o o o o o o o o o 7 o o o o o o o o o o o o o o o o o o 6 5 4 o o o o o o o o o o o o o o o o o o 3 o o o o o o o o o o o o o o o o o o 2 1 o o o o a b c d e f g h j k l m n p r s t u 10 v dd gnd gnd v dd 9 8 gnd v dd cmd v dd gnd gnda gnda v dd v dd gnd gnd v dd v dd gnd gnd vcmos v dd gnd 7 v dd dqa8 dqa7 dqa5 dqa3 dqa1 ctmn ctm row2 row0 col3 col1 dqb1 dqb3 dqb5 dqb7 dqb8 v dd 6 5 4 gnd gnd dqa6 dqa4 dqa2 dqa0 cfm cfmn row1 col4 col2 col0 dqb0 dqb2 dqb4 dqb6 gnd gnd 3 v dd gnd sck vcmos gnd v dd gnd v dd a v ref gnd v dd gnd gnd v dd sio0 sio1 gnd v dd 2 1 v dd gnd gnd v dd a b c d e f g h j k l m n p r s t u note some signals can be applied because this pin is not connected to the inside of the chip. data sheet e0251n20 (ver. 2.0) 4 pd488588ff-c80-40 pin description signal input / output type #pins description sio0, sio1 input / output cmos note1 2 serial input/output. pins for reading from and writing to the control registers using a serial access protocol. also used for power management. cmd input cmos note1 1 command input. pins used in conjunction with sio0 and sio1 for reading from and writing to the control registers. also used for power management. sck input cmos note1 1 serial clock input. clock source used for reading from and writing to the control registers. v dd 18 supply voltage for the rdram core and interface logic. v dda 1 supply voltage for the rdram analog circuitry. v cmos 2 supply voltage for cmos input/output pins. gnd 22 ground reference for rdram core and interface. gnd a 2 ground reference for rdram analog circuitry. dqa8..dqa0 input / output rsl note2 9 data byte a. nine pins which carry a byte of read or write data between the channel and the rdram. cfm input rsl note2 1 clock from master. interface clock used for receiving rsl signals from the channel. positive polarity. cfmn input rsl note2 1 clock from master. interface clock used for receiving rsl signals from the channel. negative polarity. v ref 1 logic threshold reference voltage for rsl signals. ctmn input rsl note2 1 clock to master. interface clock used for transmitting rsl signals to the channel. negative polarity. ctm input rsl note2 1 clock to master. interface clock used for transmitting rsl signals to the channel. positive polarity. row2..row0 input rsl note2 3 row access control. three pins containing control and address information for row accesses. col4..col0 input rsl note2 5 column access control. five pins containing control and address information for column accesses. dqb8..dqb0 input / output rsl note2 9 data byte b. nine pins which carry a byte of read or write data between the channel and the rdram. total pin count per package 80 notes 1. all cmos signals are high-true ; a high voltage is a logic one and a low voltage is logic zero. 2. all rsl signals are low-true ; a low voltage is a logic one and a high voltage is logic zero. data sheet e0251n20 (ver. 2.0) 5 pd488588ff-c80-40 block diagram 11 5 5 9 rop av dr br r cmbma cop s dc bc xop m dx bx packet decode control registers devid refr prer prex prec rd, wr act dm rowr rowa packet decode colm colc colx 1:8 demux rclk rq7..rq5 or row2..row0 3 sck, cmd 2 sio0, sio1 2 1:8 demux rclk rq4..rq0 or col4..col0 5 tclk ctm dqb8..dqb0 dqa8..dqa0 ctmn rclk cfm cfmn power modes rclk tclk 1:8 demux write buffer 9 8:1 mux 9 tclk 8:1 mux 9 rclk 1:8 demux write buffer write buffer bank 0 bank 1 bank 2 bank 13 bank 14 bank 15 bank 16 bank 17 bank 18 bank 29 bank 30 bank 31 samp 0 9 9 9 9 9 9 72 72 72 internal dqa data path internal dqb data path sense amp 64x72 64x72 dram core 512x128x144 72 9 column decode & mask match match match xop decode mux row decode 9 9 mux mux samp 0/1 samp 1/2 samp 13/14 samp 14/15 samp 15 samp 16 samp 16/17 samp 17/18 samp 29/30 samp 30/31 samp 31 samp 31 samp 30/31 samp 29/30 samp 17/18 samp 16/17 samp 16 samp 15 samp 14/15 samp 13/14 samp 1/2 samp 0/1 samp 0 64x72 6 5 5 5 5 5 7 8 8 ? data sheet e0251n20 (ver. 2.0) 6 pd488588ff-c80-40 contents 1. general description......................................................................................................... ........................................8 2. packet format ............................................................................................................... .........................................10 3. field encoding summary...................................................................................................... ................................12 4. dq packet timing ............................................................................................................ ......................................14 5. colm packet to d packet mapping............................................................................................. .........................14 6. row-to-row packet interaction............................................................................................... ...........................16 7. row-to-col packet interaction ............................................................................................... ............................18 8. col-to-col packet interaction ............................................................................................... .............................19 9. col-to-row packet interaction ............................................................................................... ............................20 10. row-to-row examples ........................................................................................................ ..............................21 11. row and column cycle description ........................................................................................... .......................22 12. precharge mechanisms....................................................................................................... ................................23 13. read transaction - example................................................................................................. ..............................25 14. write transaction - example................................................................................................ ...............................26 15. write/retire - examples.................................................................................................... ...................................27 16. interleaved write - example ................................................................................................ ................................29 17. interleaved read - example ................................................................................................. ...............................30 18. interleaved rrww - example ................................................................................................. ............................31 19. control register transactions.............................................................................................. ..............................32 20. control register packets ................................................................................................... .................................33 21. initialization ............................................................................................................. .............................................34 22. control register summary................................................................................................... ...............................38 23. power state management..................................................................................................... ...............................47 24. refresh.................................................................................................................... ..............................................52 25. current and temperature control ............................................................................................ ..........................54 26. electrical conditions ...................................................................................................... .....................................55 27. timing conditions .......................................................................................................... .....................................56 28. electrical characteristics ................................................................................................. ...................................58 29. timing characteristics ..................................................................................................... ...................................58 30. rsl clocking............................................................................................................... .........................................59 31. rsl - receive timing ....................................................................................................... ...................................60 32. rsl - transmit timing...................................................................................................... ...................................61 33. cmos - receive timing...................................................................................................... .................................62 34. cmos - transmit timing ..................................................................................................... ................................64 35. rsl - domain crossing window ............................................................................................... .........................65 36. timing parameters.......................................................................................................... .....................................66 37. absolute maximum ratings ................................................................................................... .............................67 data sheet e0251n20 (ver. 2.0) 7 pd488588ff-c80-40 38. i dd - supply current profile ...................................................................................................... ...........................67 39. capacitance and inductance ................................................................................................. .............................68 40. interleaved device mode .................................................................................................... .................................70 41. glossary of terms .......................................................................................................... .....................................74 42. package drawing ............................................................................................................ .....................................76 43. recommended soldering conditions ........................................................................................... .....................77 data sheet e0251n20 (ver. 2.0) 8 pd488588ff-c80-40 1. general description the figure on page 5 is a block diagram of the pd488588. it consists of two major blocks : a ?core? block built from banks and sense amps similar to those found in other types of dram, and a direct rambus interface block which permits an external controller to access this core at up to 1.6 gb/s. control registers: the cmd, sck, sio0, and sio1 pins appear in the upper center of the block diagram. they are used to write and read a block of control registers. these registers supply the rdram configuration information to a controller and they select the operating modes of the device. the nine bit refr value is used for tracking the last refreshed row. most importantly, the five bits devid specifies the device address of the rdram on the channel. clocking: the ctm and ctmn pins (clock-to-master) generate tclk (transmit clock), the internal clock used to transmit read data. the cfm and cfmn pins (clock-from-master) generate rclk (receive clock), the internal clock signal used to receive write data and to receive the row and col pins. dqa, dqb pins: these 18 pins carry read (q) and write (d) data across the channel. they are multiplexed / de- multiplexed from / to two 72-bit data paths (running at one-eighth the data frequency) inside the rdram. banks: the 32 mbyte core of the rdram is divided into 32 one-mbyte banks, each organized as 512 rows, with each row containing 128 dualocts (2k bytes), and each dualoct containing 16 bytes. a dualoct is the smallest unit of data that can be addressed. sense amps: the rdram contains 34 sense amps. each sense amp consists of 1,024 bytes of fast storage (512 for dqa and 512 for dqb) and can hold one-half of one row of one bank of the rdram. the sense amp may hold any of the 512 half-rows of an associated bank. however, each sense amp is shared between two adjacent banks of the rdram (except for numbers 0, 15, 30, and 31). this introduces the restriction that adjacent banks may not be simultaneously accessed. rq pins: these pins carry control and address information. they are broken into two groups. rq7..rq5 are also called row2..row0, and are used primarily for controlling row accesses. rq4..rq0 are also called col4..col0, and are used primarily for controlling column accesses. row pins: the principle use of these three pins is to manage the transfer of data between the banks and the sense amps of the rdram. these pins are de-multiplexed into a 24-bit rowa (row-activate) or rowr (row-operation) packet. col pins: the principle use of these five pins is to manage the transfer of data between the dqa/dqb pins and the sense amps of the rdram. these pins are de-multiplexed into a 23-bit colc (column-operation) packet and either a 17-bit colm (mask) packet or a 17-bit colx (extended-operation) packet. act command: an act (activate) command from an rowa packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 512 byte sense amps for dqa and two for dqb). prer command: a prer (precharge) command from an rowr packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be activated. data sheet e0251n20 (ver. 2.0) 9 pd488588ff-c80-40 rd command: the rd (read) command causes one of the 128 dualocts of one of the sense amps to be transmitted on the dqa/dqb pins of the channel. wr command: the wr (write) command causes a dualoct received from the dqa/dqb data pins of the channel to be loaded into the write buffer. there is also space in the write buffer for the bc bank address and c column address information. the data in the write buffer is automatically retired (written with optional bytemask) to one of the 128 dualocts of one of the sense amps during a subsequent cop command. a retire can take place during a rd, wr, or nocop to another device, or during a wr or nocop to the same device. the write buffer will not retire during a rd to the same device. the write buffer reduces the delay needed for the internal dqa/dqb data path turn- around. prec precharge: the prec, rda and wra commands are similar to nocop, rd and wr, except that a precharge operation is performed at the end of the column operation. these commands provide a second mechanism for performing precharge. prex precharge: after a rd command, or after a wr command with no byte masking (m=0), a colx packet may be used to specify an extended operation (xop). the most important xop command is prex. this command provides a third mechanism for performing precharge. data sheet e0251n20 (ver. 2.0) 10 pd488588ff-c80-40 2. packet format figure 2-1 shows the formats of the rowa and rowr packets on the row pins. table 2-1 describes the fields which comprise these packets. dr4t and dr4f bits are encoded to contain both the dr4 device address bit and a framing bit which allows the rowa or rowr packet to be recognized by the rdram. the av (rowa/rowr packet selection) bit distinguishes between the two packet types. both the rowa and rowr packet provide a five bit device address and a four bit bank address. an rowa packet uses the remaining bits to specify a nine bit row address, and the rowr packet uses the remaining bits for an eleven bit opcode field. note the use of the ?rsvx? notation to reserve bits for future address field extension. figure 2-1 also shows the formats of the colc, colm, and colx packets on the col pins. table 2-2 describes the fields which comprise these packets. the colc packet uses the s (start) bit for framing. a colm or colx packet is aligned with this colc packet, and is also framed by the s bit. the 23 bit colc packet has a five bit device address, a four bit bank address, a six bit column address, and a four bit opcode. the colc packet specifies a read or write command, as well as some power management commands. the remaining 17 bits are interpreted as a colm (m=1) or colx (m=0) packet. a colm packet is used for a colc write command which needs bytemask control. the colm packet is associated with the colc packet from a time t rtr earlier. an colx packet may be used to specify an independent precharge command. it contains a five bit device address, a four bit bank address, and a five bit opcode. the colx packet may also be used to specify some housekeeping and power management commands. the colx packet is framed within a colc packet but is not otherwise associated with any other packet. table 2-1 field description for rowa packet and rowr packet field description dr4t, dr4f bits for framing (recognizing) a rowa or rowr packet. also encodes highest device address bit. dr3..dr0 device address for rowa or rowr packet. br4..br0 bank address for rowa or rowr packet. rsvb denotes bits ignored by the rdram. av selects between rowa packet (av=1) and rowr packet (av=0). r8..r0 row address for rowa packet. rsvr denotes bits reserved for future row address extension. rop10..rop0 opcode field for rowr packet. specifies precharge, refresh, and power management functions. table 2-2 field description for colc packet, colm packet, and colx packet field description s bit for framing (recognizing) a colc packet, and indirectly for framing colm and colx packets. dc4..dc0 device address for colc packet. bc4..bc0 bank address for colc packet. rsvb denotes bits reserved for future extension (controller drivers 0's). c6..c0 column address for colc packet. cop3..cop0 opcode field for colc packet. specifies read, write, precharge, and power management functions. m selects between colm packet (m=1) and colx packet (m=0). ma7..ma0 bytemask write control bits. 1=write, 0=no-write. ma0 controls the earliest byte on dqa8..0. mb7..mb0 bytemask write control bits. 1=write, 0=no-write. mb0 controls the earliest byte on dqb8..0. dx4..dx0 device address for colx packet. bx4..bx0 bank address for colx packet. rsvb denotes bits reserved for future extension (controller drivers 0's). xop4..xop0 opcode field for colx packet. specifies precharge, i ol control, and power management functions. data sheet e0251n20 (ver. 2.0) 11 pd488588ff-c80-40 figure 2-1 packet formats ctm/cfm col4 col3 col2 col1 col0 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 8 t 9 t 10 t 11 t 0 t 1 t 2 t 3 t 0 t 1 t 2 t 3 ma7 ma5 ma3 ma1 m=1 ma6 ma4 ma2 ma0 mb7 mb4 mb1 mb6 mb3 mb0 mb5 mb2 r2 ctm/cfm row2 dr4t dr2 br0 br3 rsvr r8 r5 row1 dr4f dr1 br1 br4 rsvr r7 r4 r1 row0 dr3 dr0 br2 rsvb av=1 r6 r3 r0 act a0 prex d0 msk (b1) prer c0 wr b1 c4 ctm/cfm col4 dc4 s=1 col3 dc3 c5 c3 col2 dc2 cop1 rsvb bc2 c2 dc1 cop0 bc4 bc1 c1 dc0 cop2 cop3 bc3 bc0 c0 col1 col0 ctm/cfm row2 row1 row0 ctm/cfm col4 col3 col2 col1 col0 rop2 dr4t dr2 br0 br3 rop10 rop8 rop5 dr4f dr1 br1 br4 rop9 rop7 rop4 rop1 dr3 dr0 br2 rsvb av=0 rop6 rop3 rop0 dx4 xop4 rsvb bx1 m=0 dx3 xop3 bx4 bx0 dx2 xop2 bx3 dx1 xop1 bx2 dx0 xop0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 rowa packet colm packet colc packet colx packet rowr packet ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t packet s=1 s=1 notes 1. the colm is associated with a previous colc, and is aligned with the present colc, indicated by the start bit (s=1) position. 2. the colx is aligned with the present colc, indicates by the start bit (s=1) position. note1 note2 c6 data sheet e0251n20 (ver. 2.0) p 12 pd488588ff-c80-40 3. field encoding summary table 3-1 shows how the six device address bits are decoded for the rowa and rowr packets. the dr4t and dr4f encoding merges a fifth device bit with a framing bit. when neither bit is asserted, the device is not selected. note that a broadcast operation is indicated when both bits are set. broadcast operation would typically be used for refresh and power management commands. if the device is selected, the dm (devicematch) signal is asserted and an act or rop command is performed. table 3-1 device field encodings for rowa packet and rowr packet dr4t dr4f device selection device match signal (dm) 1 1 all devices (broadcast) dm is set to 1 0 1 one device selected dm is set to 1 if {devid4..devid0} == {0, dr3..dr0} else dm is set to 0 1 0 one device selected dm is set to 1 if {devid4..devid0} == {1, dr3..dr0} else dm is set to 0 0 0 no packet present dm is set to 0 table 3-2 shows the encodings of the remaining fields of the rowa and rowr packets. an rowa packet is specified by asserting the av bit. this causes the specified row of the specified bank of this device to be loaded into the associated sense amps. an rowr packet is specified when av is not asserted. an 11 bit opcode field encodes a command for one of the banks of this device. the prer command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. the refa (refresh-activate) command is similar to the act command, except the row address comes from an internal register refr, and refr is incremented at the largest bank address. the refp (refresh-precharge) command is identical to a prer command. the napr, naprc, pdnr, attn, and rlxr commands are used for managing the power dissipation of the rdram and are described in more detail in ? 23. power state management ? . the tcen and tcal commands are used to adjust the output driver slew rate and they are described in more detail in ? 25. current and temperature control ? . table 3-2 rowa packet and rowr packet field encodings dm av rop10..rop0 field name command description note1 10 9 8 7 6 5 4 3 2 : 0 0 ? ? ? ? ? ? ? ? ? --- ? no operation. 1 1 row address act activate row r8..r0 of bank br4..br0 of device and move device to attn note2 . 1 0 1 1 0 0 0 x note3 x x 000 prer precharge bank br4..br0 of this device. 1 0 0 0 0 1 1 0 0 x 000 refa refresh (activate) row refr8..refr0 of bank br3..br0 of device. increment refr if br4..br0=11111 (see figure 24-1). 1 0 1 0 1 0 1 0 0 x 000 refp precharge bank br4..br0 of this device after refa (see figure 24-1). 1 0 x x 0 0 0 0 1 x 000 pdnr move this device into the powerdown (pdn) power state (see figure 23-3). 1 0 x x 0 0 0 1 0 x 000 napr move this device into the nap (nap) power state (see figure 23-3). 1 0 x x 0 0 0 1 1 x 000 naprc move this device into the nap (nap) power state conditionally. 1 0 x x x x x x x 0 000 attn note2 move this device into the attention (attn) power state (see figure 23-1). 1 0 x x x x x x x 1 000 rlxr move this device into the standby (stby) power state (see figure 23-2). 1 0 0 0 0 0 0 0 0 x 001 tcal temperature calibrate this device (see figure 25-2). 1 0 0 0 0 0 0 0 0 x 010 tcen temperature calibrate/enable this device (see figure 25-2). 1 0 0 0 0 0 0 0 0 0 000 norop no operation. notes 1. the dm (device match signal) value is determined by the dr4t, dr4f, dr3..dr0 field of the rowa and rowr packets. see table 3-1. 2. the attn command does not cause a rlx-to-attn transition for a broadcast operation (dr4t/dr4f=1/1). 3. an ? x ? entry indicates which commands may be combined. for instance, the three commands prer/naprc/rlxr may be specified in one rop value (011000111000). data sheet e0251n20 (ver. 2.0) 13 pd488588ff-c80-40 table 3-3 shows the cop field encoding. the device must be in the attn power state in order to receive colc packets. the colc packet is used primarily to specify rd (read) and wr (write) commands. retire operations (moving data from the write buffer to a sense amp) happen automatically. see figure 15-1 for a more detailed description. the colc packet can also specify a prec command, which precharges a bank and its associated sense amps. the rda/wra commands are equivalent to a combining rd/wr with a prec. rlxc (relax) performs a power mode transition. see 23. power state management . table 3-3 colc packet field encodings s dc4..dc0 (select device) note1 cop3..0 name command description 0 - - - - - - - - - ? no operation. 1 /= (devid4..0) - - - - - ? retire write buffer of this device. 1 == (devid4..0) x000 note2 nocop retire write buffer of this device. 1 == (devid4..0) x001 wr retire write buffer of this device, then write column c6..c0 of bank bc4..bc0 to write buffer. 1 == (devid4..0) x010 rsrv reserved, no operation. 1 == (devid4..0) x011 rd read column c6..c0 of bank bc4..bc0 of this device. 1 == (devid4..0) x100 prec retire write buffer of this device, then precharge bank bc4..bc0 (see figure 12-2). 1 == (devid4..0) x101 wra same as wr, but precharge bank bc4..bc0 after write buffer (with new data) is retired. 1 == (devid4..0) x110 rsrv reserved, no operation. 1 == (devid4..0) x111 rda same as rd, but precharge bank bc4..bc0 afterward. 1 == (devid4..0) 1xxx rlxc move this device into the st andby (stby) power state (see figure 23-2). notes 1. ? /= ? means not equal, ? == ? means equal. 2. an ? x ? entry indicates which commands may be combined. for instance, the two commands wr/rlxc may be specified in one cop value(1001). table 3-4 shows the colm and colx field encodings. the m bit is asserted to specify a colm packet with two 8 bit bytemask fields ma and mb. if the m bit is not asserted, an colx is specified. it has device and bank address fields, and an opcode field. the primary use of the colx packet is to permit an independent prex (precharge) command to be specified without consuming control bandwidth on the row pins. it is also used for the cal (calibrate) and sam (sample) current control commands (see 25. current and temperature control ), and for the rlxx power mode command (see 23. power state management ). table 3-4 colm packet and colx packet field encodings m dx4..dx0 (select device) xop4..0 name command description 1 - - - - - msk mb/ma bytemasks used by wr/wra. 0 /= (devid4..0) - ? no operation. 0 == (devid4..0) 00000 noxop no operation. 0 == (devid4..0) 1xxx0 note prex precharge bank bx4..bx0 of this device (see figure 12-2). 0 == (devid4..0) x10x0 cal calibrate (drive) i ol current for this device (see figure 25-1). 0 == (devid4..0) x11x0 cal / sam calibrate (drive) and sample (update) i ol current for this device (see figure 25-1). 0 == (devid4..0) xxx10 rlxx move this device into the standby (stby) power state (see figure 23-2). 0 == (devid4..0) xxxx1 rsrv reserved, no operation. note an ? x ? entry indicates which commands may be combined. for instance, the two commands prex/rlxx may be specified in one xop value (10010). data sheet e0251n20 (ver. 2.0) p 14 pd488588ff-c80-40 4. dq packet timing figure 4-1 shows the timing relationship of colc packets with d and q data packets. this document uses a specific convention for measuring time intervals between packets: all packets on the row and col pins (rowa, rowr, colc, colm, colx) use the trailing edge of the packet as a reference point, and all packets on the dqa/dqb pins (d and q) use the leading edge of the packet as a reference point. an rd or rda command will transmit a dualoct of read data q a time t cac later. this time includes one to five cycles of round-trip propagation delay on the channel. the t cac parameter may be programmed to a one of a range of values (7, 8, 9, 10, 11, or 12 t cycle ). the value chosen depends upon the number of rdram devices on the channel and the rdram timing bin. see figure 22-1(5/7) ? tparm register ? for more information. a wr or wra command will receive a dualoct of write data d a time t cwd later. this time does not need to include the round-trip propagation time of the channel since the colc and d packets are traveling in the same direction. when a q packet follows a d packet (shown in the left half of the figure), a gap (t cac -t cwd ) will automatically appear between them because the t cwd value is always less than the t cac value. there will be no gap between the two colc packets with the wr and rd commands which schedule the d and q packets. when a d packet follows a q packet (shown in the right half of the figure), no gap is needed between them because the t cwd value is less than the t cac value. however, a gap of t cac - t cwd or greater must be inserted between the colc packets with the rd wr commands by the controller so the q and d packets do not overlap. figure 4-1 read (q) and write (d) data packet - timing for t cac = 7,8,9,10,11 or 12 t cycle ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 rd b1 wr a1 d (a1) t cwd rd c1 this gap on the dqa/dqb pins appears automatically this gap on the col pins must be inserted by the controller t cac t cac t cac -t cwd t cwd q (b1) wr d1 q (c1) d (d1) t cac -t cwd 5. colm packet to d packet mapping figure 5-1 shows a write operation initiated by a wr command in a colc packet. if a subset of the 16 bytes of write data are to be written, then a colm packet is transmitted on the col pins a time t rtr after the colc packet containing the wr command. the m bit of the colm packet is set to indicate that it contains the ma and mb mask fields. note that this colm packet is aligned with the colc packet which causes the write buffer to be retired. see figure 15-1 for more details. if all 16 bytes of the d data packet are to be written, then no further control information is required. the packet slot that would have been used by the colm packet (t rtr after the colc packet) is available to be used as an colx packet. this could be used for a prex precharge command or for a housekeeping command (this case is not shown). the m bit is not asserted in an colx packet and causes all 16 bytes of the previous wr to be written unconditionally. note that a rd command will never need a colm packet, and will always be able to use the colx packet option (a read operation has no need for the byte-write-enable control bits). the figure 5-1 also shows the mapping between the ma and mb fields of the colm packet and bytes of the d packet on the dqa and dqb pins. each mask bit controls whether a byte of data is written (=1) or not written (=0). data sheet e0251n20 (ver. 2.0) 15 pd488588ff-c80-40 figure 5-1 mapping between colm packet and d packet for wr command 9 , w e l t ln lx lb et n y w l vl / , e t n , l / w t y e 9 x66t x66t ,0000 00066t e0000 00066t t , x le l y b lw e / lt l, w n ll ly l/ et e, ex ln el ey eb lx ee e/ wt lb ew en wl we w/ ,t ,, ww wn ,l ,y w, wx ,e ,/ wy wb ,w ,n 0)lp 0)lp 0l 0)lp 0t 0t 0u00 t0v077 l0v077l w0v07 lb et el ee 9 x n l t nl x ln e/ wy ,y yw /e n l/ ey w, ,, ye /l nt l lt lb ex wn ,/ yy /, t b lx en w/ ,y y, /w 0 0e x n l t 0 t nl x ln e/ wy ,y yw /e n l/ ey w, ,, ye /l nt l lt lb ex wn ,/ yy /, t b lx en w/ ,y y, /w t l l e e w w , , y y / / n n 0000n66t00 00)vlp0000 )vtp0000000 000000006 0000n66t00 00)vlp0000 )vtp000000 000000006 0vl700000 0000 00600 0vt700000 06 data sheet e0251n20 (ver. 2.0) p 16 pd488588ff-c80-40 6. row-to-row packet interaction figure 6-1 shows two packets on the row pins separated by an interval t rrdelay which depends upon the packet contents. no other row packets are sent to banks {ba, ba+1, ba-1} between packet ? a ? and packet ? b ? unless noted otherwise. figure 6-1 row-to-row packet interaction - timing ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t t 17 t 18 t 19 transaction a: ropa transaction b: ropb a0 = {da,ba,ra} b0= {db,bb,rb} t rrdelay ropa a0 ropb b0 table 6-1 summarizes the t rrdelay values for all possible cases. cases rr1 through rr4 show two successive act commands. in case rr1, there is no restriction since the act commands are to different devices. in case rr2, the t rr restriction applies to the same device with non-adjacent banks. cases rr3 and rr4 are illegal (as shown) since bank ba needs to be precharged. if a prer to ba, ba+1, or ba-1 is inserted, t rrdelay is t rc (t ras to the prer command, and t rp to the next act). cases rr5 through rr8 show an act command followed by a prer command. in cases rr5 and rr6, there are no restrictions since the commands are to different devices or to non-adjacent banks of the same device. in cases rr7 and rr8, the t ras restriction means the activated bank must wait before it can be precharged. cases rr9 through rr12 show a prer command followed by an act command. in cases rr9 and rr10, there are essentially no restrictions since the commands are to different devices or to non-adjacent banks of the same device. rr10a and rr10b depend upon whether a bracketed bank (ba+-1) is precharged or activated. in cases rr11 and rr12, the same and adjacent banks must all wait t rp for the sense amp and bank to precharge before being activated. cases rr13 through rr16 summarize the combinations of two successive prer commands. in case rr13 there is no restriction since two devices are addressed. in rr14, t pp applies, since the same device is addressed. in rr15 and rr16, the same bank or an adjacent bank may be given repeated prer commands with only the t pp restriction. two adjacent banks can ? t be activate simultaneously. a precharge command to one bank will thus affect the state of the adjacent banks (and sense amps). if bank ba is activate and a prer is directed to ba, then bank ba will be precharged along with sense amps ba-1/ba and ba/ba+1. if bank ba+1 is activate and a prer is directed to ba, then bank ba+1 will be precharged along with sense amps ba/ba+1 and ba+1/ba+2. if bank ba-1 is activate and a prer is directed to ba, then bank ba-1 will be precharged along with sense amps ba/ba-1 and ba-1/ba-2. a row packet may contain commands other than act or prer. the refa and refp commands are equivalent to act and prer for interaction analysis purposes. the interaction rules of the napr, naprc, pdnr, rlxr, attn, tcal, and tcen commands are discussed in later section (see table 3-2 for cross-ref). data sheet e0251n20 (ver. 2.0) 17 pd488588ff-c80-40 table 6-1 row-to-row packet interaction - rules case # ropa da ba ra ropb db bb rb t rrdelay example rr1 act da ba ra act /= da xxxx x..x t packet figure 10-2 rr2 act da ba ra act == da /= {ba, ba+1, ba-1} x..x t rr figure 10-2 rr3 act da ba ra act == da == {ba+1, ba-1} x..x t rc - illegal unless prer to ba / ba+1 / ba-1 figure 10-1 rr4 act da ba ra act == da == {ba} x..x t rc - illegal unless prer to ba / ba+1 / ba-1 figure 10-1 rr5 act da ba ra prer /= da xxxx x..x t packet figure 10-2 rr6 act da ba ra prer == da /= {ba, ba+1, ba-1} x..x t packet figure 10-2 rr7 act da ba ra prer == da == {ba+1, ba-1} x..x t ras figure 10-1 rr8 act da ba ra prer == da == {ba} x..x t ras figure 13-1 rr9 prer da ba ra act /= da xxxx x..x t packet figure 10-3 rr10 prer da ba ra act == da /= {ba, ba+-1, ba+-2} x..x t packet figure 10-3 rr10a prer da ba ra act == da == {ba+2} x..x t packet /t rp if ba+1 is precharged/activated. rr10b prer da ba ra act == da == {ba-2} x..x t packet /t rp if ba-1 is precharged/activated. rr11 prer da ba ra act == da == {ba+1, ba-1} x..x t rp figure 10-1 rr12 prer da ba ra act == da == {ba} x..x t rp figure 10-1 rr13 prer da ba ra prer /= da xxxx x..x t packet figure 10-3 rr14 prer da ba ra prer == da /= {ba, ba+1, ba-1} x..x t pp figure 10-3 rr15 prer da ba ra prer == da == {ba+1, ba-1} x..x t pp figure 10-3 rr16 prer da ba ra prer == da == {ba} x..x t pp figure 10-3 data sheet e0251n20 (ver. 2.0) p 18 pd488588ff-c80-40 7. row-to-col packet interaction figure 7-1 shows two packets on the row and col pins. they must be separated by an interval t rcdelay which depends upon the packet contents. figure 7-1 row-to-col packet interaction- timing ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t t 17 t 18 t 19 transaction a: ropa transaction b: copb a0 = {da,ba,ra} b1= {db,bb,cb1} t rcdelay ropa a0 copb b1 table 7-1 summarizes the t rcdelay values for all possible cases. note that if the col packet is earlier than the row packet, it is considered a col-to-row packet interaction. cases rc1 through rc5 summarize the rules when the row packet has an act command. figure 13-1 and figure 14-1 show examples of rc5 - an activation followed by a read or write. rc4 is an illegal situation, since a read or write of a precharged banks is being attempted (remember that for a bank to be activated, adjacent banks must be precharged). in cases rc1, rc2, and rc3, there is no interaction of the row and col packets. cases rc6 through rc8 summarize the rules when the row packet has a prer command. there is either no interaction (rc6 through rc9) or an illegal situation with a read or write of a precharged bank (rc9). the col pins can also schedule a precharge operation with a rda, wra, or prec command in a colc packet or a prex command in a colx packet. the constraints of these precharge operations may be converted to equivalent prer command constraints using the rules summarized in figure 12-2. table 7-1 row-to-col packet interaction - rules case # ropa da ba ra copb db bb cb1 t rcdelay example rc1 act da ba ra nocop, rd, retire /= da xxxx x..x 0 rc2 act da ba ra nocop == da xxxx x..x 0 rc3 act da ba ra rd, retire == da /= {ba, ba+1, ba-1} x..x 0 rc4 act da ba ra rd, retire == da == {ba+1, ba-1} x..x illegal rc5 act da ba ra rd, retire == da == {ba} x..x t rcd figure 13-1 rc6 prer da ba ra nocop, rd, retire /= da xxxx x..x 0 rc7 prer da ba ra nocop == da xxxx x..x 0 rc8 prer da ba ra rd, retire == da /= {ba, ba+1, ba-1} x..x 0 rc9 prer da ba ra rd, retire == da == {ba+1, ba-1} x..x illegal data sheet e0251n20 (ver. 2.0) 19 pd488588ff-c80-40 8. col-to-col packet interaction figure 8-1 shows three arbitrary packets on the col pins. packets ? b ? and ? c ? must be separated by an interval t ccdelay which depends upon the command and address values in all three packets. table 8-1 summarizes the t ccdelay values for all possible cases. cases cc1 through cc5 summarize the rules for every situation other than the case when copb is a wr command and copc is a rd command. in cc3, when a rd command is followed by a wr command, a gap of t cac - t cwd must be inserted between the two col packets. see figure 4-1 for more explanation of why this gap is needed. for cases cc1, cc2, cc4, and cc5, there is no restriction (t ccdelay is t cc ). in cases cc6 through cc10, copb is a wr command and copc is a rd command. the t ccdelay value needed between these two packets depends upon the command and address in the packet with copa. in particular, in case cc6 when there is wr-wr-rd command sequence directed to the same device, a gap will be needed between the packets with copb and copc. the gap will need a colc packet with a nocop command directed to any device in order to force an automatic retire to take place. figure 15-2 (right) provides a more detailed explanation of this case. in case cc10, there is a rd-wr-rd sequence directed to the same device. if a prior write to the same device is unretired when copa is issued, then a gap will be needed between the packets with copb and copc as in case cc6. the gap will need a colc packet with a nocop command directed to any device in order to force an automatic retire to take place. cases cc7, cc8, and cc9 have no restriction (t ccdelay is t cc ). for the purposes of analyzing col-to-row interactions, the prec, wra, and rda commands of the colc packet are equivalent to the nocop, wr, and rd commands. these commands also cause a precharge operation prec to take place. this precharge may be converted to an equivalent prer command on the row pins using the rules summarized in figure 12-2. table 8-1 col-to-col packet interaction - rules case # copa da ba ca1 copb db bb cb1 copc dc bc cc1 t ccdelay example cc1 xxxx xxxxx x..x x..x nocop db bb cb1 xxxx xxxxx x..x x..x t cc cc2 xxxx xxxxx x..x x..x rd, wr db bb cb1 nocop xxxxx x..x x..x t cc cc3 xxxx xxxxx x..x x..x rd db bb cb1 wr xxxxx x..x x..x t cc + t cac - t cwd figure 4-1 cc4 xxxx xxxxx x..x x..x rd db bb cb1 rd xxxxx x..x x..x t cc figure 13-1 cc5 xxxx xxxxx x..x x..x wr db bb cb1 wr xxxxx x..x x..x t cc figure 14-1 cc6 wr == db x x..x wr db bb cb1 rd == db x..x x..x t rtr figure 15-1 cc7 wr == db x x..x wr db bb cb1 rd /= db x..x x..x t cc cc8 wr /= db x x..x wr db bb cb1 rd == db x..x x..x t cc cc9 nocop == db x x..x wr db bb cb1 rd == db x..x x..x t cc cc10 rd == db x x..x wr db bb cb1 rd == db x..x x..x t cc figure 8-1 col-to-col packet interaction- timing wyhw*y oCb6cct oC36cct w<[4pppp pppccw<[t ^<-pppp pppcc^ data sheet e0251n20 (ver. 2.0) p 22 pd488588ff-c80-40 figure 10-3 shows examples of the prer-to-prer (rr13, rr14) and prer-to-act (rr9, rr10) command spacings from table 6-1. the rr15 and rr16 cases (prer-to-prer to same or adjacent banks) are not shown, but are similar to rr14. in general, the commands in row packets may be spaced an interval t packet apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both prer or both act) directed to the same device. figure 10-3 row packet example ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 prer a0 act b0 t packet prer c0 t pp a0 = {da,ba,ra} b0 = {db,bb,rb} c0 = {da,bc,rc} different device any bank same device non-adjacent bank rr13 rr14 prer a0 prer a0 prer b0 act c0 t packet t packet b0 = {db,bb,rb} c0 = {da,bc,rc} different device any bank same device non-adjacent bank rr9 rr10 prer a0 c0 = {da,ba,rc} same device ajacent bank rr15 c0 = {da,ba+1rc} same device same bank rr16 11. row and column cycle description activate: a row cycle begins with the activate (act) operation. the activation process is destructive; the act of sensing the value of a bit in a bank ? s storage cell transfers the bit to the sense amp, but leaves the original bit in the storage cell with an incorrect value. restore: because the activation process is destructive, a hidden operation called restore is automatically performed. the restore operation rewrites the bits in the sense amp back into the storage cells of the activated row of the bank. read/write: while the restore operation takes place, the sense amp may be read (rd) and written (wr) using column operations. if new data is written into the sense amp, it is automatically forwarded to the storage cells of the bank so the data in the activated row and the data in the sense amp remain identical. precharge: when both the restore operation and the column operations are completed, the sense amp and bank are precharged (pre). this leaves them in the proper state to begin another activate operation. intervals: the activate operation requires the interval t rcd,min to complete. the hidden restore operation requires the interval t ras,min - t rcd,min to complete. column read and write operations are also performed during the t ras,min - t rcd,min interval (if more than about four column operations are performed, this interval must be increased). the precharge operation requires the interval t rp,min to complete. adjacent banks: an rdram with a ? s ? designation (512k x 18 x 32s) indicates it contains ? split banks ? . this means the sense amps are shared between two adjacent banks. the only exception is that sense amp 0, 15, 30, and 31 are not shared. when a row in a bank is activated, the two adjacent sense amps are connected to (associated with) that bank and are not available for use by the two adjacent banks. these two adjacent banks must remain precharged while the selected bank goes through its activate, restore, read/write, and precharge operations. for example (referring to the block diagram), if bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will both be loaded with one of the 512 rows (with 1,024 bytes loaded into each sense amp from the 2k byte row ? 512 bytes to the dqa side and 512 bytes to the dqb side). while this row from bank 5 is being accessed, no rows may be accessed in banks 4 or 6 because of the sense amp sharing. data sheet e0251n20 (ver. 2.0) 23 pd488588ff-c80-40 12. precharge mechanisms figure 12-1 shows an example of precharge with the rowr packet mechanism. the prer command must occur a time t ras after the act command, and a time t rp before the next act command. this timing will serve as a baseline against which the other precharge mechanisms can be compared. figure 12-1 precharge via prer command in rowr packet ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 act a0 prer a5 t ras t rc a0 = {da,ba,ra} a5 = {da,ba} b0 = {da,ba,rb} t rp act b0 figure 12-2 (top) shows an example of precharge with a rda command. a bank is activated with an rowa packet on the row pins. then, a series of four dualocts are read with rd commands in colc packets on the col pins. the fourth of these commands is a rda, which causes the bank to automatically precharge when the final read has finished. the timing of this automatic precharge is equivalent to a prer command in an rowr packet on the row pins that is offset a time t offp from the colc packet with the rda command. the rda command should be treated as a rd command in a colc packet as well as a simultaneous (but offset) prer command in an rowr packet when analyzing interactions with other packets. figure 12-2 (middle) shows an example of precharge with a wra command. as in the rda example, a bank is activated with an rowa packet on the row pins. then, two dualocts are written with wr commands in colc packets on the col pins. the second of these commands is a wra, which causes the bank to automatically precharge when the final write has been retired. the timing of this automatic precharge is equivalent to a prer command in an rowr packet on the row pins that is offset a time t offp from the colc packet that causes the automatic retire. the wra command should be treated as a wr command in a colc packet as well as a simultaneous (but offset) prer command in an rowr packet when analyzing interactions with other packets. note that the automatic retire is triggered by a colc packet a time t rtr after the colc packet with the wr command unless the second colc contains a rd command to the same device. this is described in more detail in figure 15- 1. figure 12-2 (bottom) shows an example of precharge with a prex command in an colx packet. a bank is activated with an rowa packet on the row pins. then, a series of four dualocts are read with rd commands in colc packets on the col pins. the fourth of these colc packets includes an colx packet with a prex command. this causes the bank to precharge with timing equivalent to a prer command in an rowr packet on the row pins that is offset a time t offp from the colx packet with the prex command. data sheet e0251n20 (ver. 2.0) p 24 pd488588ff-c80-40 figure 12-2 offsets for alternate precharge mechanisms ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 rd a1 act a0 rd a2 q (a2) q (a1) act b0 msk (a2) msk (a1) retire (a1) t offp wr a1 d (a2) d (a1) act b0 act a0 transaction a: rd a0 = {da,ba,ra} a5 = {da,ba} colc packet: rda precharge offset colc packet: wda precharge offset transaction a: wr a0 = {da,ba,ra} a1 = {da,ba,ca1} a2 = {da,ba,ca2} a5 = {da,ba} colx packet: prex precharge offset rd a3 q (a4) q (a3) rda a4 prer a5 the rda precharge is equivalent to a prer command here t offp prer a5 the wra precharge (triggered by the automatic retire) is equivalent to a prer command here wra a2 retire (a2) t rtr a3 = {da,ba,ca3} a4 = {da,ba,ca4} a1 = {da,ba,ca1} a2 = {da,ba,ca2} rd a1 act a0 rd a2 q (a2) q (a1) act b0 t offp transaction a: rd a0 = {da,ba,ra} a5 = {da,ba} rd a3 q (a4) q (a3) prer a5 the prex precharge command is equivalent to a prer command here a3 = {da,ba,ca3} a4 = {da,ba,ca4} a1 = {da,ba,ca1} a2 = {da,ba,ca2} rd a4 prex a5 data sheet e0251n20 (ver. 2.0) 25 pd488588ff-c80-40 13. read transaction - example figure 13-1 shows an example of a read transaction. it begins by activating a bank with an act a0 command in an rowa packet. a time t rcd later a rd a1 command is issued in a colc packet. note that the act command includes the device, bank, and row address (abbreviated as a0) while the rd command includes device, bank, and column address (abbreviated as a1). a time t cac after the rd command the read data dualoct q (a1) is returned by the device. note that the packets on the row and col pins use the end of the packet as a timing reference point, while the packets on the dqa/dqb pins use the beginning of the packet as a timing reference point. a time t cc after the first colc packet on the col pins a second is issued. it contains a rd a2 command. the a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. a time t cac after the second rd command a second read data dualoct q(a2) is returned by the device. next, a prer a3 command is issued in an rowr packet on the row pins. this causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. the a3 address includes the same device and bank address as the a0, a1, and a2 addresses. the prer command must occur a time t ras or more after the original act command (the activation operation in any dram is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the t ras interval). the prer command must also occur a time t rdp or more after the last rd command. note that the t rdp value shown is greater than the t rdp,min specification in ? 36.timing parameters ? . this transaction example reads two dualocts, but there is actually enough time to read three dualocts before t rdp becomes the limiting parameter rather than t ras . if four dualocts were read, the packet with prer would need to shift right (be delayed) by one t cycle (note-this case is not shown). finally, an act b0 command is issued in an rowr packet on the row pins. the second act command must occur a time t rc or more after the first act command and a time t rp or more after the prer command. this ensures that the bank and its associated sense amps are precharged. this example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. transaction b may not be started until transaction a has finished. however, transactions to other banks or other devices may be issued during transaction a. figure 13-1 read transaction example ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 rd a1 act a0 prer a3 rd a2 q (a2) t rcd t cac t cc q (a1) act b0 t ras t rc t rp transaction a: rd a0 = {da,ba,ra} a1 = {da,ba,ca1} a2 = {da,ba,ca2} a3 = {da,ba} t cac t rdp transaction b: xx b0 = {da,ba,rb} data sheet e0251n20 (ver. 2.0) p 26 pd488588ff-c80-40 14. write transaction - example figure 14-1 shows an example of a write transaction. it begins by activating a bank with an act a0 command in an rowa packet. a time t rcd - t rtr later a wr a1 command is issued in a colc packet (note that the t rcd interval is measured to the end of the colc packet with the first retire command). note that the act command includes the device, bank, and row address (abbreviated as a0) while the wr command includes device, bank, and column address (abbreviated as a1). a time t cwd after the wr command the write data dualoct d(a1) is issued. note that the packets on the row and col pins use the end of the packet as a timing reference point, while the packets on the dqa/dqb pins use the beginning of the packet as a timing reference point. a time t cc after the first colc packet on the col pins a second colc packet is issued. it contains a wr a2 command. the a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. a time t cwd after the second wr command a second write data dualoct d(a2) is issued. a time t rtr after each wr command an optional colm packet msk (a1) is issued, and at the same time a colc packet is issued causing the write buffer to automatically retire. see figure 15-1 for more detail on the write/retire mechanism. if a colm packet is not used, all data bytes are unconditionally written. if the colc packet which causes the write buffer to retire is delayed, then the colm packet (if used) must also be delayed. next, a prer a3 command is issued in an rowr packet on the row pins. this causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. the a3 address includes the same device and bank address as the a0, a1, and a2 addresses. the prer command must occur a time t ras or more after the original act command (the activation operation in any dram is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the t ras interval). a prer a3 command is issued in an rowr packet on the row pins. the prer command must occur a time t rtp or more after the last colc which causes an automatic retire. finally, an act b0 command is issued in an rowr packet on the row pins. the second act command must occur a time t rc or more after the first act command and a time t rp or more after the prer command. this ensures that the bank and its associated sense amps are precharged. this example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. transaction b may not be started until transaction a has finished. however, transactions to other banks or other devices may be issued during transaction a. figure 14-1 write transaction example ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 msk (a2) retire (a2) msk (a1) retire (a1) wr a1 prer a3 wr a2 d (a2) d (a1) act b0 t rc t rp act a0 t cwd transaction a: wr a0 = {da,ba,ra} a1 = {da,ba,ca1} a2 = {da,ba,ca2} a3 = {da,ba} t cc t cwd t rtr t ras t rtr t rtp transaction b: xx b0 = {da,ba,rb} rcd t data sheet e0251n20 (ver. 2.0) 27 pd488588ff-c80-40 15. write/retire - examples the process of writing a dualoct into a sense amp of an rdram bank occurs in two steps. the first step consists of transporting the write command, write address, and write data into the write buffer. the second step happens when the rdram automatically retires the write buffer (with an optional bytemask) into the sense amp. this two-step write process reduces the natural turn-around delay due to the internal bidirectional data pins. figure 15-1 (left) shows an example of this two step process. the first colc packet contains the wr command and an address specifying device, bank and column. the write data dualoct follows a time t cwd later. this information is loaded into the write buffer of the specified device. the colc packet which follows a time t rtr later will retire the write buffer. the retire will happen automatically unless (1) a colc packet is not framed (no colc packet is present and the s bit is zero), or (2) the colc packet contains a rd command to the same device. if the retire does not take place at time t rtr after the original wr command, then the device continues to frame colc packets, looking for the first that is not a rd directed to itself. a bytemask msk(a1) may be supplied in a colm packet aligned with the colc that retires the write buffer at time t rtr after the wr command. the memory controller must be aware of this two-step write/retire process. controller performance can be improved, but only if the controller design accounts for several side effects. figure 15-1 (right) shows the first of these side effects. the first colc packet has a wr command which loads the address and data into the write buffer. the third colc causes an automatic retire of the write buffer to the sense amp. the second and fourth colc packets (which bracket the retire packet) contain rd commands with the same device, bank and column address as the original wr command. in other words, the same dualoct address that is written is read both before and after it is actually retired. the first rd returns the old dualoct value from the sense amp before it is overwritten. the second rd returns the new dualoct value that was just written. figure 15-1 normal retire (left) and retire/read ordering (right) ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 22 t 19 t 23 transaction a: wr a1= {da,ba,ca1} d (a1) wr a1 ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 22 t 19 t 23 transaction a: wr transaction b: rd a1= {da,ba,ca1} b1= {da,ba,ca1} retire (a1) msk (a1) t rtr t cwd d (a1) wr a1 retire (a1) msk (a1) t rtr rd b1 rd c1 q (b1) t cwd transaction c: rd c1= {da,ba,ca1} t cac this rd gets the old data this rd gets the new data retire is automatic here unless: t cac (1) no colc packet (s=0) or (2) colc packet is rd to device da q ( figure 15-2 (left) shows the result of performing a rd command to the same device in the same colc packet slot that would normally be used for the retire operation. the read may be to any bank and column address; all that matters is that it is to the same device as the wr command. the retire operation and msk(a1) will be delayed by a time t packet as a result. if the rd command used the same bank and column address as the wr command, the old data from the sense amp would be returned. if many rd commands to the same device were issued instead of the single one that is shown, then the retire operation would be held off an arbitrarily long time. however, once a rd to another device or a wr or nocop to any device is issued, the retire will take place. figure 15-2 (right) illustrates a situation in which the controller wants to issue a wr-wr-rd colc packet sequence, with all commands addressed to the same device, but addressed to any combination of banks and columns. the rd will prevent a retire of the first wr from automatically happening. but the first dualoct d(a1) in the write data sheet e0251n20 (ver. 2.0) p 28 pd488588ff-c80-40 buffer will be overwritten by the second wr dualoct d(b1) if the rd command is issued in the third colc packet. therefore, it is required in this situation that the controller issue a nocop command in the third colc packet, delaying the rd command by a time of t packet . this situation is explicitly shown in table 8-1 for the cases in which t ccdelay is equal to t rtr . figure 15-2 retire held off by read (left) and controller forces wwr gap (right) ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 22 t 19 t 23 transaction a: wr transaction b: rd a1= {da,ba,ca1} b1= {da,bb,cb1} transaction a: wr transaction b: wr a1= {da,ba,ca1} b1= {da,bb,cb1} d (a1) wr a1 retire (a1) msk (a1) rd b1 q (b1) t cwd t cac ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 18 t 19 d (a1) wr a1 rd c1 t rtr retire (a1) msk (a1) t cwd t cac wr b1 d (b1) transaction c: rd c1= {da,bc,cc1} the controller must insert a nocop to retire (a1) to make room for the data (b1) in the write buffer the retire operation for a write can be held off by a read to the same device t rtr + t packet figure 15-3 shows a possible result when a retire is held off for a long time (an extended version of figure 15-2-left). after a wr command, a series of six rd commands are issued to the same device (but to any combination of bank and column addresses). in the meantime, the bank ba to which the wr command was originally directed is precharged, and a different row rc is activated. when the retire is automatically performed, it is made to this new row, since the write buffer only contains the bank and column address, not the row address. the controller can insure that this doesn ? t happen by never precharging a bank with an unretired write buffer. note that in a system with more than one rdram, there will never be more than two rdrams with unretired write buffers. this is because a wr command issued to one device automatically retires the write buffers of all other devices written a time t rtr before or earlier. figure 15-3 retire held off by reads to same device, write buffer retired to new row ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 msk (a1) retire (a1) rd b1 wr a1 prer a2 t rcd act c0 t ras t rc t rp act a0 t cwd t rtr transaction a: wr a0 = {da,ba,ra} a1 = {da,ba,ca1} a2 = {da,ba} rd b2 rd b3 rd b4 rd b5 rd b6 transaction b: rd b1 = {da,bb,cb1} b2 = {da,bb,cb2} b3= {da,bb,cb3} b4 = {da,bb,cb4} b5 = {da,bb,cb5} b6 = {da,bb,cb6} q (b1) t cac q (b2) q (b3) q (b4) q (b5) transaction c: wr c0 = {da,ba,rc} d (a1) the retire operation puts the write data in the new row warning this sequence is hazardous and must be used with caution data sheet e0251n20 (ver. 2.0) 29 pd488588ff-c80-40 16. interleaved write - example figure 16-1 shows an example of an interleaved write transaction. transactions similar to the one presented in figure 14-1 are directed to non-adjacent banks of a single rdram. this allows a new transaction to be issued once every t rr interval rather than once every t rc interval (four times more often). the dq data pin efficiency is 100% with this sequence. with two dualocts of data written per transaction, the col, dqa, and dqb pins are fully utilized. banks are precharged using the wra autoprecharge option rather than the prer command in an rowr packet on the row pins. in this example, the first transaction is directed to device da and bank ba. the next three transactions are directed to the same device da, but need to use different, non-adjacent banks bb, bc, bd so there is no bank conflict. the fifth transaction could be redirected back to bank ba without interference, since the first transaction would have completed by then (t rc has elapsed). each transaction may use any value of row address (ra, rb, ...) and column address (ca1, ca2, cb1, cb2, ...). figure 16-1 interleaved write transaction with two dualoct data length ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 act a0 msk (b2) wra c2 msk (b1) wr c1 wr b1 msk (a1) wra b2 msk (a2) d (b2) d (b1) act b0 act c0 act d0 act e0 d (a2) d (a1) wr d1 msk (c1) d(c1) act f0 wr d2 msk (c2) wr e1 msk (d1) d (c2) d (d1) wr e2 msk (d2) d (z2) d (z1) d (x2) d (y1) d (y2) msk (z2) wra a2 msk (z1) wr a1 wr z1 msk (y1) wra z2 msk (y2) q ( t rcd t cwd t rc transaction e can use the same bank as transaction a t rr f3 = {da,ba+2} transaction f: wr f0 = {da,ba+2,rf} f1 = {da,ba+2,cf1} f2= {da,ba+2,cf2} e3 = {da,ba} transaction e: wr e0 = {da,ba,re} e1 = {da,ba,ce1} e2= {da,ba,ce2} d3 = {da,ba+6} transaction d: wr d0 = {da,ba+6,rd} d1 = {da,ba+6,cd1} d2= {da,ba+6,cd2} c3 = {da,ba+4} transaction c: wr c0 = {da,ba+4,rc} c1 = {da,ba+4,cc1} c2= {da,ba+4,cc2} b3 = {da,ba+2} transaction b: wr b0 = {da,ba+2,rb} b1 = {da,ba+2,cb1} b2= {da,ba+2,cb2} a3 = {da,ba} transaction a: wr a0 = {da,ba,ra} a1 = {da,ba,ca1} a2= {da,ba,ca2} z3 = {da,ba+6} transaction z: wr z0 = {da,ba+6,rz} z1 = {da,ba+6,cz1} z2= {da,ba+6,cz2} y3 = {da,ba+4} transaction y: wr y0 = {da,ba+4,ry} y1 = {da,ba+4,cy1} y2= {da,ba+4,cy2} data sheet e0251n20 (ver. 2.0) p 30 pd488588ff-c80-40 17. interleaved read - example figure 17-1 shows an example of interleaved read transactions. transactions similar to the one presented in figure 13-1 are directed to non-adjacent banks of a single rdram. the address sequence is identical to the one used in the previous write example. the dq data pins efficiency is also 100%. the only difference with the write example (aside from the use of the rd command rather than the wr command) is the use of the prex command in a colx packet to precharge the banks rather than the rda command. this is done because the prex is available for a readtransaction but is not available for a masked write transaction. figure 17-1 interleaved read transaction with two dualoct data length ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 act a0 prex b3 rd c2 rd c1 rd b1 rd b2 prex a3 act b0 act c0 act d0 act e0 rd a1 rd a2 prex z3 rd d1 rdd2 prex c3 rd e1 rd e2 prex d3 rd z1 rd z2 prex y3 q (b2) q (b1) q (a2) q (a1) q (c1) q (c2) q (d1) q (z2) q (z1) q (x2) q (y1) q (y2) t rcd t cac transaction e can use the same bank as transaction a t rc t rr f3 = {da,ba+2} transaction f: rd f0 = {da,ba+2,rf} f1 = {da,ba+2,cf1} f2= {da,ba+2,cf2} e3 = {da,ba} transaction e: rd e0 = {da,ba,re} e1 = {da,ba,ce1} e2= {da,ba,ce2} d3 = {da,ba+6} transaction d: rd d0 = {da,ba+6,rd} d1 = {da,ba+6,cd1} d2= {da,ba+6,cd2} c3 = {da,ba+4} transaction c: rd c0 = {da,ba+4,rc} c1 = {da,ba+4,cc1} c2= {da,ba+4,cc2} b3 = {da,ba+2} transaction b: rd b0 = {da,ba+2,rb} b1 = {da,ba+2,cb1} b2= {da,ba+2,cb2} a3 = {da,ba} transaction a: rd a0 = {da,ba,ra} a1 = {da,ba,ca1} a2= {da,ba,ca2} z3 = {da,ba+6} transaction z: rd z0 = {da,ba+6,rz} z1 = {da,ba+6,cz1} z2= {da,ba+6,cz2} y3 = {da,ba+4} transaction y: rd y0 = {da,ba+4,ry} y1 = {da,ba+4,cy1} y2= {da,ba+4,cy2} act f0 data sheet e0251n20 (ver. 2.0) 31 pd488588ff-c80-40 18. interleaved rrww - example figure 18-1 shows a steady-state sequence of 2-dualoct rd/rd/wr/wr.. transactions directed to non-adjacent banks of a single rdram. this is similar to the interleaved write and read examples in figure 16-1 and figure 17-1 except that bubble cycles need to be inserted by the controller at read/write boundaries. the dq data pin efficiency for the example in figure 18-1 is 32/42 or 76%. if there were more rdrams on the channel, the dq pin efficiency would approach 32/34 or 94% for the two-dualoct rrww sequence (this case is not shown). in figure 18-1, the first bubble type t cbub1 is inserted by the controller between a rd and wr command on the col pins. this bubble accounts for the round-trip propagation delay that is seen by read data, and is explained in detail in figure 4-1. this bubble appears on the dqa and dqb pins as t dbub1 between a write data dualoct d and read data dualoct q. this bubble also appears on the row pins as t rbub1 . the second bubble type t cbub2 is inserted (as a nocop command) by the controller between a wr and rd command on the col pins when there is a wr-wr-rd sequence to the same device. this bubble enables write data to be retired from the write buffer without being lost, and is explained in detail in figure 15-2. there would be no bubble if address c0 and address d0 were directed to different devices. this bubble appears on the dqa and dqb pins as t dbub2 between a write data dualoct d and read data dualoct q. this bubble also appears on the row pins as t rbub2 . figure 18-1 interleaved rrww sequence with two dualoct data length ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 act a0 msk (b2) wra c2 msk (b1) wr c1 wr b1 msk (y2) wra b2 prex a3 d (b2) d (b1) act b0 act c0 act d0 act e0 rd a1 rd a2 prex z3 q (a2) q (a1) msk (c1) d (c1) nocop rdd0 d (c2) t rbub1 rd f q (z2) q (z1) d (y2) rd z1 rd z2 t cbub1 t dbub1 t dbub1 t dbub2 t cbub2 t rbub2 t cbub2 nocop f3 = {da,ba+2} transaction f: wr f0 = {da,ba+2,rf} f1 = {da,ba+2,cf1} f2= {da,ba+2,cf2} e3 = {da,ba} transaction e: rd e0 = {da,ba,re} e1 = {da,ba,ce1} e2= {da,ba,ce2} d3 = {da,ba+6} transaction d: rd d0 = {da,ba+6,rd} d1 = {da,ba+6,cd1} d2= {da,ba+6,cd2} c3 = {da,ba+4} transaction c: wr c0 = {da,ba+4,rc} c1 = {da,ba+4,cc1} c2= {da,ba+4,cc2} b3 = {da,ba+2} transaction b: wr b0 = {da,ba+2,rb} b1 = {da,ba+2,cb1} b2= {da,ba+2,cb2} a3 = {da,ba} transaction a: rd a0 = {da,ba,ra} a1 = {da,ba,ca1} a2= {da,ba,ca2} z3 = {da,ba+6} transaction z: rd z0 = {da,ba+6,rz} z1 = {da,ba+6,cz1} z2= {da,ba+6,cz2} y3 = {da,ba+4} transaction y: wr y0 = {da,ba+4,ry} y1 = {da,ba+4,cy1} y2= {da,ba+4,cy2} transaction e can use the same bank as transaction a msk (c2) data sheet e0251n20 (ver. 2.0) p 32 pd488588ff-c80-40 19. control register transactions the rdram has two cmos input pins sck and cmd and two cmos input/output pins sio0 and sio1. these provide serial access to a set of control registers in the rdram. these control registers provide configuration information to the controller during the initialization process. they also allow an application to select the appropriate operating mode of the rdram. sck (serial clock) and cmd (command) are driven by the controller to all rdrams in parallel. sio0 and sio1 are connected (in a daisy chain fashion) from one rdram to the next. in normal operation, the data on sio0 is repeated on sio1, which connects to sio0 of the next rdram (the data is repeated from sio1 to sio0 for a read data packet). the controller connects to sio0 of the first rdram. write and read transactions are each composed of four packets, as shown in figure 19-1 and figure 19-2. each packet consists of 16 bits, as summarized in table 20-1 and table 20-2. the packet bits are sampled on the falling edge of sck. a transaction begins with a srq (serial request) packet. this packet is framed with a 11110000 pattern on the cmd input (note that the cmd bits are sampled on both the falling edge and the rising edge of sck). the srq packet contains the sop3..sop0 (serial opcode) field, which selects the transaction type. the sdev5..sdev0 (serial device address) selects one of the 32 rdrams. if sbc (serial broadcast) is set, then all rdrams are selected. the sa (serial address) packet contains a 12 bit address for selecting a control register. a write transaction has a sd (serial data) packet next. this contains 16 bits of data that is written into the selected control register. a sint (serial interval) packet is last, providing some delay for any side-effects to take place. a read transaction has a sint packet, then a sd packet. this provides delay for the selected rdram to access the control register. the sd read data packet travels in the opposite direction (towards the controller) from the other packet types. the sck cycle time will accommodate the total delay. figure 19-1 serial write (swr) transaction to control register srq - swr command 1111 00000000...00000000 srq - swr command 0000 sa sa sd sd sint sint 00000000...00000000 00000000...00000000 00000000...00000000 sck cmd sio0 sio1 t 4 t 36 t 20 t 52 t 68 each packet is repeated from sio0 to sio1 1 1 1 1 0 0 0 0 1111 next transaction figure 19-2 serial read (srd) transaction control register srq - srd command 1111 00000000...00000000 srq - srd command 0000 sa sa sint sint sd sd 00000000...00000000 00000000...00000000 00000000...00000000 sck cmd sio 0 sio 1 t 4 t 36 t 20 t 52 t 68 first 3 packets are repeated from sio0 to sio1 1 1 1 1 0 0 0 0 1111 next transaction 0 0 addressed rdram devices 0/sd15..sd0/0 on sio0 controller drives 0 on sio0 non addressed rdrams pass 0/sd15..sd0/0 from sio1 to sio0 0 0 data sheet e0251n20 (ver. 2.0) 33 pd488588ff-c80-40 20. control register packets 0 000et.l00000000 00006000et.e0 0000000060 000et.l000000070 7000600000 000070000000 0006000000 0000070600000 000000000 0060 0 table 20-1 control register packet formats sck cycle sio0 or sio1 for srq sio0 or sio1 for sa sio0 or sio1 for sint sio0 or sio1 for sd sck cycle sio0 or sio1 for srq sio0 or sio1 for sa sio0 or sio1 for sint sio0 or sio1 for sd 0 rsrv rsrv 0 sd15 8 sop1 sa7 0 sd7 1 rsrv rsrv 0 sd14 9 sop0 sa6 0 sd6 2 rsrv rsrv 0 sd13 10 sbc sa5 0 sd5 3 rsrv rsrv 0 sd12 11 sdev4 sa4 0 sd4 4 rsrv sa11 0 sd11 12 sdev3 sa3 0 sd3 5 sdev5 sa10 0 sd10 13 sdev2 sa2 0 sd2 6 sop3 sa9 0 sd9 14 sdev1 sa1 0 sd1 7 sop2 sa8 0 sd8 15 sdev0 sa0 0 sd0 table 20-2 field description for control register packets field description rsrv reserved. should be driven as ? 0 ? by controller. sop3..sop0 0000 - srd. serial read of control register {sa11..sa0} of rdram {sdev5..sdev0}. 0001 - swr. serial write of control register {sa11..sa0} of rdram {sdev5..sdev0}. 0010 - setr. set reset bit, all control registers assume their reset values. note 16 t scycle delay until clrr command. 0100 - setf. set fast (normal) clock mode. 4 t scycle delay until next command. 1011 - clrr. clear reset bit, all control registers retain their reset values. note 4 t scycle delay until next command. 1111 - nop. no serial operation. 0011, 0101 ? 1010, 1100 ? 1110 ? rsrv. reserved encodings. sdev5..sdev0 serial device. compared to sdevid5..sdevid0 field of init control register field to select the rdram to which the transaction is directed. sbc serial broadcast. when set, rdrams ignore {sdev5..sdev0} for rdram selection. sa11..sa0 serial address. selects which control register of the selected rdram is read or written. sd15..sd0 serial data. the 16 bits of data written to or read from the selected control register of the selected rdram. note the setr and clrr commands must always be applied in two successive transactions to rdrams; i.e. they may not be used in isolation. this is called ? setr/clrr reset ? . figure 20-1 setr, clrr, setf transaction t et 00.099 llll tttttttt666tttttttt 00.099 tttt l , 000 0t00l0 l l l l t t t t data sheet e0251n20 (ver. 2.0) p 34 pd488588ff-c80-40 21. initialization figure 21-1 sio pin reset sequence sck cmd sio0 t 16 0000000000000000 00000000...00000000 0000000000000000 sio1 t 0 the packet is repeated from sio0 to sio1 1 1 1 1 0 0 0 0 00001100 initialization refers to the process that a controller must go through after power is applied to the system or the system is reset. the controller prepares the rdram sub-system for normal channel operation by (primarily) using a sequence of control register transactions on the serial cmos pins. the following steps outline the sequence seen by the various memory subsystem components (including the rdram components) during initialization. this sequence is available in the form of reference code. contact rambus inc. for more information. 1.0 start clocks this step calculates the proper clock frequencies for pclk (controller logic), synclk (rac block), refclk (drcg component), ctm (rdram component), and sck (sio block). 2.0 rac initialization this step causes the init block to generate a sequence of pulses which resets the rac, performs rac maintainance operations, and measures timing intervals in order to ensure clock stability. 3.0 rdram initialization this stage performs most of the steps needed to initialize the rdrams. the rest are performed in stages 5.0, 6.0, and 7.0. all of the steps in 3.0 are carried out through the sio block interface. 3.1/3.2 sio reset after a delay of t pause from step 1.0, this reset operation is performed before any sio control register read or write transactions. it clears six registers (test34, cca, ccb, skip, test78, and test79) and places the init register into a special state (all bits cleared except skp and sdevid fields are set to ones). 3.3 write test77 register the test77 register must be explicitly written with zeros before any other registers are read or written. 3.4 write tcycle register the tcycle register is written with the cycle time t cycle of the ctm clock (for channel and rdrams) in units of 64ps. the t cycle value is determined in stage 1.0. 3.5 write sdevid register the sdevid (serial device identification) register of the rdram is written with a unique address value so that directed sio read and write transactions can be performed. this address value increases from 0 to 31 according to the distance an rdram is from the asic component on the sio bus (the closest rdram is address 0). data sheet e0251n20 (ver. 2.0) 35 pd488588ff-c80-40 3.6 write devid register the devid (device identification) register of the rdram is written with a unique address value so that directed memory read and write transactions can be performed. this address value increases from 0 to 31. the devid value is not necessarily the same as the sdevid value. rdrams are sorted into regions of the same core configuration (number of bank, row, and column address bits and core type). 3.7 write pdnx, pdnxa registers the pdnx and pdnxa registers are written with values that are used to measure the timing intervals connected with an exit from the pdn (powerdown) power state. 3.8 write napx register the napx register is written with values that are used to measure the timing intervals connected with an exit from the nap power state. 3.9 write tparm register the tparm register is written with values which determine the time interval between a col packet with a memory read command and the q packet with the read data on the channel. the values written set the rdram to the minimum value permitted for the system. this will be adjusted later in stage 6.0. 3.10 write tcdly1 register the tcdly1 register is written with values which determine the time interval between a col packet with a memory read command and the q packet with the read data on the channel. the values written set the rdram to the minimum value permitted for the system. this will be adjusted later in stage 6.0. 3.11 write tfrm register the tfrm register is written with a value that is related to the t rcd parameter for the system. the t rcd parameter is the time interval between a row packet with an activate command and the col packet with a read or write command. 3.12 setr/clrr first write the following registers with the indicated values: test78 0004 16 test34 0040 16 next, the rdram is given a setr command and a clrr command through the sio block. this sequence performs a second reset operation on the rdrams. then the test34 and test78 registers are rewritten with zero, in that order. 3.13 write cca and ccb registers these registers are written with a value halfway between their minimum and maximum values. this shortens the time needed for the rdrams to reach their steady-state current control values in stage 5.0. 3.14 powerdown exit the rdram is in the pdn power state at this point. a broadcast pdnexit command is performed by the sio block to place the rdrams in the rlx (relax) power state in which they are ready to receive row packets. 3.15 setf the rdram is given a setf command through the sio block. one of the operations performed by this step is to generate a value for the as (autoskip) bit in the skip register and fix the rdram to a particular read domain. data sheet e0251n20 (ver. 2.0) p 36 pd488588ff-c80-40 4.0 controller configuration this stage initializes the controller block. each step of this stage will set a field of the configrmc[63:0] bus to the appropriate value. other controller implementations will have similar initialization requirements, and this stage may be used as a guide. 4.1 initial read data offset the configrmc bus is written with a value which determines the time interval between a col packet with a memory read command and the q packet with the read data on the channel. the value written sets rmc.d1 to the minimum value permitted for the system. this will be adjusted later in stage 6.0. 4.2 configure row/column timing this step determines the values of the t ras,min , t rp,min , t rc,min , t rcd,min , t rr,min , and t pp,min rdram timing parameters that are present in the system. the configrmc bus is written with values that will be compatible with all rdram devices that are present. 4.3 set refresh interval this step determines the values of the t ref,max rdram timing parameter that are present in the system. the configrmc bus is written with a value that will be compatible with all rdram devices that are present. 4.4 set current control interval this step determines the values of the t cctrl,max rdram timing parameter that are present in the system. the configrmc bus is written with a value that will be compatible with all rdram devices that are present. 4.5 set slew rate control interval this step determines the values of the t temp,max rdram timing parameter that are present in the system. the configrmc bus is written with a value that will be compatible with all rdram devices that are present. 4.6 set bank/row/col address bits this step determines the number of rdram bank, row, and column address bits that are present in the system. it also determines the rdram core types (independent, doubled, or split) that are present. the configrmc bus is written with a value that will be compatible with all rdram devices that are present. 5.0 rdram current control this step causes the init block to generate a sequence of pulses which performs rdram maintenance operations. 6.0 rdram core, read domain initialization this stage completes the rdram initialization 6.1 rdram core initialization a sequence of 192 memory refresh transactions is performed in order to place the cores of all rdrams into the proper operating state. 6.2 rdram read domain initialization a memory write and memory read transaction is performed to the rdram to determine which read domain the rdram occupies. the programmed delay of the rdram is then adjusted so the total rdram read delay (propagation delay plus programmed delay) is constant. the tparm and tcdly1 registers of the rdram is rewritten with the appropriate read delay values. the configrmc bus is also rewritten with an updated value. data sheet e0251n20 (ver. 2.0) 37 pd488588ff-c80-40 7.0 other rdram register fields this stage rewrites the init register with the final values of the lsr, nsr, and psr fields. in essence, the controller must read all the read-only configuration registers of all rdrams (or it must read the spd device present on each rimm), it must process this information, and then it must write all the read-write registers to place the rdrams into the proper operating mode. initialization note : 1. during the initialization process, it is necessary for the controller to perform 128 current control operations (3xcal, 1xcal/sam) and one temperature calibrate operation (tcen/tcal) after reset or after powerdown (pdn) exit. 2. the behavior of data sheet e0251n20 (ver. 2.0) p 38 pd488588ff-c80-40 22. control register summary 0 000ee.l00000600000000000ee.l600 .0000000000600.0000000 0000000600 ? table 22-1 control register summary (1/2) sa11..sa0 register field read-write/ read-only description 021 16 init sdevid read-write, 6 bits serial device id. device address for control register read/write. psx read-write, 1 bit power select exit. pdn/nap exit with device addr on dqa5..0. srp read-write, 1 bit sio repeater. used to initialize rdram. nsr read-write, 1 bit nap self-refresh. enables self-refresh in nap mode. psr read-write, 1 bit pdn self-refresh. enables self-refresh in pdn mode. lsr read-write, 1 bit low power self-refresh. enables low power self-refresh. ten read-write, 1 bit temperature sensing enable. tsq read-write, 1 bit temperature sensing output. dis read-write, 1 bit rdram disable. idm read-write, 1 bit interleaved device mode enable. 022 16 test34 test34 read-write, 16 bits test register. do not read or write after sio reset. 023 16 cnfga refbit read-only, 3 bits refresh bank bits. used for multi-bank refresh. dbl read-only, 1 bit double. specifies doubled-bank architecture. mver read-only, 6 bits manufacturer version. manufacturer identification number. pver read-only, 6 bits protocol version. specifies version of direct protocol supported. 024 16 cnfgb byt read-only, 1 bit byte. specifies an 8-bit or 9-bit byte size. devtyp read-only, 3 bits device type. device can be rdram or some other device category. spt read-only, 1 bit split-core. each core half is an individual dependent core. corg read-only, 6 bits core organization. bank, row, column address field sizes. sver read-only, 6 bits stepping version. mask version number. 040 16 devid devid read-write, 5 bits device id. device address for memory read/write. 041 16 refb refb read-write, 4 bits refresh bank. next bank to be refreshed by self-refresh. 042 16 refr refr read-write, 9 bits refresh row. next row to be refreshed by refa, self-refresh. 043 16 cca cca read-write, 7 bits current control a. controls i ol output current for dqa. asyma read-write, 2 bits asymmetry control. controls asymmetry of v ol /v oh swing for dqa. 044 16 ccb ccb read-write, 7 bits current control b. controls i ol output current for dqb. asymb read-write, 2 bits asymmetry control. controls asymmetry of v ol /v oh swing for dqb. 045 16 napx napxa read-write, 5 bits nap exit. specifies length of nap exit phase a. napx read-write, 5 bits nap exit. specifies length of nap exit phase a + phase b. dqs read-write, 1 bit dq select. selects cmd framing for nap/pdn exit. 046 16 pdnxa pdnxa read-write, 13 bits pdn exit. specifies length of pdn exit phase a. data sheet e0251n20 (ver. 2.0) 39 pd488588ff-c80-40 table 22-1 control register summary (2/2) sa11..sa0 register field read-write/ read-only description 047 16 pdnx pdnx read-write, 13 bits pdn exit. specifies length of pdn exit phase a + phase b. 048 16 tparm tcas read-write, 2 bits t cas-c core parameter. determines t offp datasheet parameter. tcls read-write, 2 bits t cls-c core parameter. determines t cac and t offp parameters. tcdly0 read-write, 3 bits t cdly0-c core parameter. programmable delay for read data. 049 16 tfrm tfrm read-write, 4 bits t frm-c core parameter. determines row - col packet framing interval. 04a 16 tcdly1 tcdly1 read-write, 3 bits t cdly-1 core parameter. programmable delay for read data. 04c 16 tcycle tcycle read-write, 14 bits t cycle datasheet parameter. specifies cycle time in 64ps units. 04b 16 skip as read-only, 1 bit autoskip value established by the setf command. mse read-write, 1 bit manual skip enable. allows the ms value to override the as value. ms read-write, 1 bit manual skip value. 04d 16 - test77 test77 read-write, 16 bits test register. write with zero after sio reset. 04e 16 - test78 test78 read-write, 16 bits test register. do not read or write after sio reset. 04f 16 - test79 test79 read-write, 16 bits test register. do not read or write after sio reset. 080 16 -off 16 reserved reserved vendor-specific vendor-specific test registers. do not read or write after sio reset. data sheet e0251n20 (ver. 2.0) p 40 pd488588ff-c80-40 figure 22-1 control registers (1/7) control register : init address : 021 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 idm sde vid5 dis tsq ten lsr psr nsr srp psx 0 sdevid4..0 read/write register. reset values are undefined except as affected by sio reset as noted below. setr/clrr reset does not affect this register. field description reset value sdevid5..0 serial device identification. compared to sdevid5..0 serial address field of serial request packet for register read/write transactions. this determines which rdram is selected for the register read or write operation. 3f 16 dis rdram disable. dis=1 causes rdram to ignore nap/pdn exit sequence, dis=0 permit normal operation. this mechanism disables an rdram. 0 tsq temperature sensing output. tsq=1 when a temperature trip point has been exceeded, tsq=0 when it has not. tsq is available during a current control operation (see figure 25-1). ten temperature sensing enable. ten=1 enables temperature sensing circuitry, permitting the tsq bit to be read to determine if a thermal trip point has been exceeded. 0 lsr low power self-refresh. this function is not supported. lsr value must be 0. 0 psr pdn self-refresh. psr=1 enables self-refresh in pdn mode. psr can ? t be set while in pdn mode. 0 nsr nap self-refresh. nsr=1 enables self-refresh in nap mode. nsr can ? t be set while in nap mode. 0 srp sio repeater. controls value on sio1; sio1=sio0 if srp=1, sio1=1 if srp=0. 1 psx power exit select. pdn and nap are exited with (=0) or without (=1) a device address on the dqa5..0 pins. pdev5 (on dqa5) selectes broadcast (1) or directed (0) exit. for a dircted exit, pdev4..0 (on dqa4..0) is compared to devid4..0 to select a device. control register : cnfga address : 023 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pver5..0=000001 mver5..0= mmmmmm dbl1 refbit2..0=101 read only register. field description pver5..0 protocol version. specifies the direct protocol version used by this device: 0 ? reserved 1 ? version 1 protocol. 2 ? version 1 plus interleaved device mode. 3 to 63 ? reserved mver5..0 manufacturer version. specifies the manufacturer identification number. dbl doubled-bank. dbl=1 means the device uses a doubled-bank architecture with adjacent-bank dependency. dbl=0 means no dependency. refbit2..0 refresh bank bits. specifies the number of bank address bits used by refa and refp commands. permits multi-bank refresh in future rdrams. caution in rdrams with protocol version 1 pver[5:0] =000001, the range of the pdnx field (pdnx[2:0] in the pdnx register) may not be large enough to specify the location of the restricted interval in figure 23-3. in this case, the effective t s4 parameter must increase and no row or column packets may overlap the restricted interval. see figure 23-3 and timing conditions table. data sheet e0251n20 (ver. 2.0) 41 pd488588ff-c80-40 figure 22-1 control registers (2/7) control register : cnfgb address : 024 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sver5..0=ssssss corg4..0=01000 spt0 devtyp2..0=000 bytb read only register. field description sver5..0 stepping version. specifies the mask version number of this device. corg4..0 core organization. this field specifies the number of bank (5 bits), row (9 bits), and column (7 bits) address bits. spt split-core. spt=1 means the core is split, spt=0 means it is not. devtyp2..0 device type. devtyp=000 means that this device is an rdram. byt byte width. b=1 means the device reads and writes 9-bit memory bytes.b=0 means 8 bits. control register : test34 address : 022 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 read/write register. reset values of test34 is zero (from sio reset). this register are used for testing purposes. it must not be read or written after sio reset. control register : devid address : 040 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 devid4..0 read/write register. reset value is undefined. field description devid4..0 device identification register. devid4..devid0 is compared to dr4..dr0, dc4..dc0, and dx4..dx0 fields for all memory read or write transactions. this determines which rdram is selected for the memory read or write transaction. data sheet e0251n20 (ver. 2.0) p 42 pd488588ff-c80-40 figure 22-1 control registers (3/7) control register : refb address : 041 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 refb4..0 read/write register. field description reset value refb4..0 refresh bank register. refb4..refb0 is the bank that will be refreshed next during self-refresh. refb4..0 is incremented after each self-refresh activate and precharge operation pair. 0 control register : refr address : 042 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 refr8..0 read/write register. field description reset value refr8..0 refresh row register. refr8..refr0 is the row that will be refreshed next by the refa command or by self-refresh. refr8..0 is incremented when br4..0=11111 for the refa command. refr8..0 is incremented when refb4..0=11111 for self-refresh. 0 control register : cca address : 043 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 asym a0 cca6..0 read/write register. field description reset value asyma0 control the asymmetry of the v ol /v oh voltage swing about the v ref reference voltage for the dqa8..0 pins. asyma0 odf 0 0.00 1 0.12 asyma0 where odf is the over drive factor (the extra i ol current sunk by an rsl output when asyma0 is set). cca6..0 current control a. controls the i ol output current for the dqa8..dqa0 pins. 0 control register : ccb address : 044 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 asym b0 ccb6..0 read/write register. field description reset value asymb0 control the asymmetry of the v ol /v oh voltage swing about the v ref reference voltage for the dqb8..0 pins. asymb0 odf 0 0.00 1 0.12 asymb0 where odf is the over drive factor (the extra i ol current sunk by an rsl output when asymb0 is set). ccb6..0 current control b. controls the i ol output current for the dqb8..dqb0 pins. 0 data sheet e0251n20 (ver. 2.0) 43 pd488588ff-c80-40 figure 22-1 control registers (4/7) control register : napx address : 045 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 dqs napx4..0 napxa4..0 read/write register. reset value is undefined. note t scycle is t cycle1 (sck cycle time). field description dqs dq select. this field specifies the number of sck cycles (0 ? 1 ? for this rdram. napx4..0 nap exit phase a plus b. this field specifies the number of sck cycles during the first plus sec ond phases for exiting nap mode. it must satisfy: napx ? ? ? control register : pdnxa address : 046 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 pdnxa12..0 read/write register. reset value is undefined. field description pdnxa4..0 pdn exit phase a. this field specifies the number of (64 ? ? ? ? only pdnxa4..0 are implemented. note ? t scycle is t cycle1 (sck cycle time). control register : pdnx address : 047 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 pdnx12..0 read/write register. reset value is undefined. field description pdnx2..0 pdn exit phase a puls b. this field specifies the number of (256 ? ? ? ? ? ? t be satisfied, then the maximum pdnx value should be written, and the t s4 / t h4 timing window will be modified (see figure 23-4). do not set this field to zero. note ? only pdnx2..0 are implemented. note ? t scycle is t cycle1 (sck cycle time). data sheet e0251n20 (ver. 2.0) p 44 pd488588ff-c80-40 figure 22-1 control registers (5/7) control register : tparm address : 048 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 tcdly0 tcls tcal read/write register. reset value is undefined. field description tcdly0 specifies the t cdly0-c core parameter in t cycle units. this adds a programmable delay to q (read data) packets, permitting round trip read delay to all device to be equalized. this field may be written with the values ? 010 ? (2 ? ? 101 ? (5 ? ? 10 ? (2 ? ? 10 ? (2 ? ? ? ? ? ? ? ? t cls-c =t rcd-c - 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? control register : tfrm address : 049 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 tfrm3..0 read/write register. reset value is undefined. field description tfrm3..0 specifies the position of the framing point in t cycle units. this value must be greater than or equal to the t frm,min parameter. this is the minimum offset between a row packet (which places a device at attn) and the first col packet (directed to that device) which must be framed. this field may be written with the value ? 0111 ? (7 ? ? 1010 ? (10 ? ? ? ? data sheet e0251n20 (ver. 2.0) 45 pd488588ff-c80-40 figure 22-1 control registers (6/7) control register : tcdly1 address : 04a 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tcdly1 read/write register. reset value is undefined. field description tcdly1 specifies the value of the t cdly1-c core parameter in t cycle units. this adds a programmable delay to q (read data) packets, permitting round trip read to delay all devices to be equalized. this field may be written with the values ? 000 ? (0 ? ? 010 ? (2 ? control register : skip address : 04b 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 as mse ms 0 0 0 0 0 0 0 0 0 0 read/write register (except as field). reset value is zero (sio reset). field description ms manual skip (ms must be 1 when mse=1). > during initialization, the rdrams at the furthest point in the fifth read domain may have selected the as=0 value, placing them at the closest point in a sixth read domain. setting the mse/ms fields to 1/1 overrides the autoskip value and returns them to the furthest point of the fifth read domain. mse manual skip enable (0=auto, 1=manual ). as autoskip. read-only value determined by autoskip circuit and stored when setf serial command is received by rdram during initialization. in figure34-1, as=1 corresponds to the early q(a1) packet and as=0 to the q(a1) packet one t cycle later for the four uncertain cases. control register : tcycle address : 04c 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 tcycle13..0 read/write register. reset value is undefined. field description tcycle13..0 specifies the value of the t cycle datasheet parameter in 64ps units. for the t cycle,min of 2.50 ns (2500ps), this field should be written with the value ? 00027 16 ? (39 ? data sheet e0251n20 (ver. 2.0) p 46 pd488588ff-c80-40 figure 22-1 control registers (7/7) 0 control register : test77 address : 04d 16 control register : test78 address : 04e 16 control register : test79 address : 04f 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 read/write register. field description reset value test77 it must be written with zero after sio reset. these registers must only be used for testing purposes. ? data sheet e0251n20 (ver. 2.0) 47 pd488588ff-c80-40 23. power state management table 23-1 summarizes the power states available to a direct rdram. in general, the lowest power states have the longest operational latencies. for example, the relative power levels of pdn state and stby state have a ratio of about 1:110, and the relative access latencies to get read data have a ratio of about 250:1. pdn state is the lowest power state available. the information in the rdram core is usually maintained with self- refresh; an internal timer automatically refreshes all rows of all banks. pdn has a relatively long exit latency because the tclk/rclk block must resynchronize itself to the external clock signal. nap state is another low-power state in which either self-refresh or refa-refresh are used to maintain the core. see 24. refresh for a description of the two refresh mechanisms. nap has a shorter exit latency than pdn because the tclk/rclk block maintains its synchronization state relative to the external clock signal at the time of nap entry. this imposes a limit (t nlimit ) on how long an rdram may remain in nap state before briefly returning to stby or attn to update this synchronization state. table 23-1 power state summary power state description blocks consuming power power state description blocks consuming power pdn powerdown state. self-refresh nap nap state. similar to pdn except lower wake-up latency. self-refresh or refa-refresh tclk/rclk-nap stby standby state. ready for row packets. refa-refresh tclk/rclk row demux receiver attn attention state. ready for row and col packets. refa-refresh tclk/rclk row demux receiver col demux receiver attnr attention read state. ready for row and col packets. sending q (read data) packets. refa-refresh tclk/rclk row demux receiver col demux receiver dq mux transmitter core power attnw attention write state. ready for row and col packets. ready for d (write data) packets. refa-refresh tclk/rclk row demux receiver col demux receiver dq demux receiver core power data sheet e0251n20 (ver. 2.0) p 48 pd488588ff-c80-40 figure 23-1 summarizes the transition conditions needed for moving between the various power states. note that nap and pdn have been divided into two substates (nap-a/nap-s and pdn-a/pdn-s) to account for the fact that a nap or pdn exit may be made to either attn or stby states. figure 23-1 power state transition diagram automatic automatic automatic automatic automatic automatic attnr attnw attn stby setr/clrr nap-a napr rlxr notation: setr/clrr - setr/clrr reset sequence in srq packet pdnr - pdnr command in rowr packet napr - napr command in rowr packet rlxr - rlx command in rowr packet rlx - rlx command in rowr,colc,colx packets sio0 - sio0 input value pdev.cmd - (pdev=devid) (cmd=01) attn - rowa packet(non-broadcast) or rowr packet (non-broadcast) with attn command t nlimit nap nap-s pdev.cmd sio0 napr rlxr pdev.cmd sio0 pdn-a pdnr rlxr pdn pdn-s pdev.cmd sio0 pdnr rlxr pdev.cmd sio0 napr pdnr attn rlx at initialization, the setr/clrr reset sequence will put the rdram into pdn-s state. the pdn exit sequence involves an optional pdev specification and bits on the cmd and sio in pins. once the rdram is in stby, it will move to the attn/attnr/attnw states when it receives a non-broadcast rowa packet or non-broadcast rowr packet with the attn command. the rdram returns to stby from these three states when it receives a rlx command. alternatively, it may enter nap or pdn state from attn or stby states with a napr or pdnr command in an rowr packet. the pdn or nap exit sequence involves an optional pdev specification and bits on the cmd and sio0 pins. the rdram returns to the attn or stby state it was originally in when it first entered nap or pdn. an rdram may only remain in nap state for a time t nlimit . it must periodically return to attn or stby. the naprc command causes a napdown operation if the rdram ? s ncbit is set. the ncbit is not directly visible. it is undefined on reset. it is set by a napr command to the rdram, and it is cleared by an act command to the rdram. it permits a controller to manage a set of rdrams in a mixture of power states. stby state is the normal idle state of the rdram. in this state all banks and sense amps have usually been left precharged and rowa and rowr packets on the row pins are being monitored. when a non-broadcast rowa packet or non-broadcast rowr packet(with the attn command) packet addressed to the rdram is seen, the rdram enters attn state (see the right side of figure 23-2). this requires a time t sa during which the rdram activates the specified row of the specified bank. a time tfrm ? ? see figure 22-1(5/7) ? tfrm register ? ). once in attn state, the rdram will automatically transition to the attnw and attnr states as it receives wr and rd commands. data sheet e0251n20 (ver. 2.0) 49 pd488588ff-c80-40 once the rdram is in attn, attnw, or attnr states, it will remain there until it is explicitly returned to the stby state with a rlx command. a rlx command may be given in an rowr, colc, or colx packet (see the left side of figure 23-2). it is usually given after all banks of the rdram have been precharged; if other banks are still activated, then the rlx command would probably not be given. if a broadcast rowa packet or rowr packet (with the attn command) is received, the rdram ? s power state doesn ? t change. if a broadcast rowr packet with rlxr command is received, the rdram goes to stby. figure 23-2 stby entry (left) and stby exit (right) stby attn ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 22 t 19 t 23 ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t as rlxr power state attn power state stby t sa rop a0 rlxc rlxx tfrm t cycle cop a1 cop a1 cop a1 cop a1 xop a1 cop a0 xop a0 rop=non-broadcast r owa or rowr/attn a0={d0, b0, r0} a 1={d1, b1, c1} no col packets may b e placed in the thre e indicated positions; i.e. a t (tfrm-{1,2,3}) t cycle . a col packet to device d0 ( or any other device) is okay at (tfrm) t cycle or later. a col packet to another device (d1!=d0 ) is okay at (tfrm-4) t cycle or earlier. figure 23-3 shows the nap entry sequence (left). nap state is entered by sending a napr command in a row packet. a time t asn is required to enter nap state (this specification is provided for power calculation purposes). the clock on ctm/cfm must remain stable for a time t cd after the napr command. figure 23-3 nap entry (left) and pdn entry (right) ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 22 t 19 t 23 ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t asn rop a0 (napr) power state attn/stby note power state nap attn/stby note pdn t asp rop a0 (pdnr) note the(eventual) nap/pdn exit will be to the same attn/stby state the rdram was in prior to nap/pdn entry t cd t cd a0={d0, b0, r0, c0} a 1={d1, b1, c1, c1} no row or col packets directed to device d0 may overlap the restricted interval. no broadcast row packets may overlap the quiet interval. row or col packets to a device other than d0 may overlap the restricted interval. restricted rop a1 cop a0 xop a0 cop a1 xop a1 restricted restricted rop a1 cop a0 xop a0 cop a1 xop a1 restricted row or col packets directed to device d0 after the restricted interval will be ignored. t npq t npq the rdram may be in attn or stby state when the napr command is issued. when nap state is exited, the rdram will return to the original starting state (attn or stby). if it is in attn state and a rlxr command is specified with napr, then the rdram will return to stby state when nap is exited. figure 23-3 also shows the pdn entry sequence (right). pdn state is entered by sending a pdnr command in a row packet. a time t asp is required to enter pdn state (this specification is provided for power calculation purposes). the clock on ctm/cfm must remain stable for a time t cd after the pdnr command. data sheet e0251n20 (ver. 2.0) p 50 pd488588ff-c80-40 the rdram may be in attn or stby state when the pdnr command is issued. when pdn state is exited, the rdram will return to the original starting state (attn or stby). if it is in attn state and a rlxr command is specified with pdnr, then the rdram will return to stby state when pdn is exited. the current- and slew-rate- control levels are re-established. the rdram ? s write buffer must be retired with the appropriate cop command before nap or pdn are entered. also, all the rdram ? s banks must be precharged before nap or pdn are entered. the exception to this is if nap is entered with the nsr bit of the init register cleared(disabling self-refresh in nap). the commands for relaxing, retiring, and precharging may be given to the rdram as late as the ropa0, copa0, and xopa0 packets in figure 23-3. no broadcast packets nor packets directed to the rdram entering nap or pdn may overlay the quiet window. this window extends for a time t npq after the packet with the napr or pdnr command. figure 23-4 shows the nap and pdn exit sequences. these sequences are virtually identical; the minor differences will be highlighted in the following description. before nap or pdn exit, the ctm/cfm clock must be stable for a time t ce . then, on a falling and rising edge of sck, if there is a ? 01 ? on the cmd input, nap or pdn state will be exited. also, on the falling sck edge the sio0 input must be at a 0 for nap exit and 1 for pdn exit. if the psx bit of the init register is 0, then a device pdev5..0 is specified for nap or pdn exit on the dqa5..0 pins. this value is driven on the rising sck edge 0.5 or 1.5 sck cycles after the original falling edge, depending upon the value of the dqs bit of the napx register. if the psx bit of the init register is 1, then the rdram ignores the pdev5..0 address packet and exits nap or pdn when the wake-up sequence is presented on the cmd wire. the row and col pins must be quiet at a time t s4 / t h4 around the indicated falling sck edge(timed with the pdnx or napx register fields). after that, row and col packets may be directed to the rdram which is now in attn or stby state. figure 23-5 shows the constraints for entering and exiting nap and pdn states. on the left side, an rdram exits nap state at the end of cycle t 3 . this rdram may not re-enter nap or pdn state for an interval of t nu0 . the rdram enters nap state at the end of cycle t 13 . this rdram may not re-exit nap state for an interval of t nu1 . the equations for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. napx is the value in the napx field in the napx register. on the right side of figure23-4, an rdram exits pdn state at the end of cycle t 3 . this rdram may not re-enter pdn or nap state for an interval of t pu0 . the rdram enters pdn state at the end of cycle t 13 . this rdram may not re-exit pdn state for an interval of t pu1 . the equations for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. pdnx is the value in the pdnx field in the pdnx register. data sheet e0251n20 (ver. 2.0) 51 pd488588ff-c80-40 figure 23-4 nap and pdn exit ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 rop sck cmd sio0 sio1 0 1 0/1 0/1 pdev5..0 t s3 t h3 t ce the packet is repeated from sio0 to sio1 restricted power state t s4 t h4 nap/pdn (napx t )/(256 pdnx t ) scycle t s4 t h4 cop xop notes 1. use 0 for nap exit, 1 for pdn exit 2. device selection timing slot is selected by dqs field of napx register note 1 note 1 stby/attn note 4 rop cop xop restricted no row packets may overlap the restricted interval no col packets may overlap the restricted interval if device pdev is exiting the nap-a or pdn-a states scycle 4. exit to stby or attn depends upon whether rlxr was asserted at nap or pdn entry time note 2 pdev5..0 note 2 t s3 t h3 dqs=0 dqs=1 note 2,3 note 2 dqs=0 dqs=1 note 2 note 2 if psx=1 in init register, then nap/pdn exit is broadcast (no pdev field). effective hold becomes t h4 ? = t h4 +[pdnxa ? ? ? ? ? ? ? ? 3. the dqs field must be written with ? 1 ? for this rdram. figure 23-5 nap entry/exit windows (left) and pdn entry/exit windows (right) 9 e 066t t , x le l y b lw e / lt l, w n ll ly l/ et e, t ln el ey l lx ee e/ e lb ew en w , x le l/ y b lw ln / lt l, lx n ll ly lb t0000000l 0000000vy t +(2+napx) t 0 1 ctm/cfm row2 ..row0 sck cmd pdnr pdn entry 0 1 t pu0 t pu1 no entry to nap or pdn no exit t nu0 t nu1 no entry to nap or pdn no exit cycle scycle nu0 t =8 t - (0.5 t ) cycle scycle nu1 =23 t cycle if nsr=0 if nsr=1 t =5 t +(2+256 pdnx) t cycle scycle pu0 t =8 t - (0.5 t ) cycle scycle pu1 =23 t cycle if psr=0 if psr=1 0 nap exit pdn exit nap entry data sheet e0251n20 (ver. 2.0) p 52 pd488588ff-c80-40 24. refresh rdrams, like any other dram technology, use volatile storage cells which must be periodically refreshed. this is accomplished with the refa command. figure 24-1 shows an example of this. the refa command in the transaction is typically a broadcast command (dr4t and dr4f are both set in the rowr packet), so that in all devices bank number ba is activated with row number refr, where refr is a control register in the rdram. when the command is broadcast and attn is set, the power state of the rdrams (attn or stby) will remain unchanged. the controller increments the bank address ba for the next refa command. when ba is equal to its maximum value, the rdram automatically increments refr for the next refa command. on average, these refa commands are sent once every t ref / 2 bbit+rbit (where bbit are the number of bank address bits and rbit are the number of row address bits) so that each row of each bank is refreshed once every t ref interval. the refa command is equivalent to an act command, in terms of the way that it interacts with other packets (see table 6-1). in the example, an act command is sent after t rr to address b0, a different (non-adjacent) bank than the refa command. a second act command can be sent after a time t rc to address c0, the same bank (or an adjacent bank) as the refa command. note that a broadcast refp command is issued a time t ras after the initial refa command in order to precharge the refreshed bank in all rdrams. after a bank is given a refa command, no other core operations(activate or precharge) should be issued to it until it receives a refp. it is also possible to interleave refresh transactions (not shown). in the figure, the act b0 command would be replaced by a refa b0 command. the b0 address would be broadcast to all devices, and would be {broadcast, ba+2,refr}. note that the bank address should skip by two to avoid adjacent bank interference. a possible bank incrementing pattern would be: {12, 10, 5, 3, 0, 14, 9, 7, 4, 2, 13, 11, 8, 6, 1, 15, 28, 26, 21, 19, 16, 30, 25, 23, 20, 18, 29, 27, 24, 22, 17, 31}. every time bank 31 is reached, a refa command would automatically increment the refr register. a second refresh mechanism is available for use in pdn and nap power states. this mechanism is called self- refresh mode. when the pdn power state is entered, or when nap power state is entered with the nsr control register bit set, then self-refresh is automatically started for the rdram. self-refresh uses an internal time base reference in the rdram. this causes an activate and precharge to be carried out once in every t ref / 2 bbit+rbit interval. the refb and refr control registers are used to keep track of the bank and row being refreshed. before a controller places an rdram into self-refresh mode, it should perform refa/refp refreshes until the bank address is equal to the maximum value. this ensures that no rows are skipped. likewise, when a controller returns an rdram to refa/refp refresh, it should start with the minimum bank address value (zero). figure 24-2 illustrates the requirement imposed by the t burst parameter. after pdn or nap (when self-refresh is enabled) power states are exited, the controller must refresh all banks of the rdram once during the interval t burst after the restricted interval on the row and col buses. this will ensure that regardless of the state of self-refresh during pdn or nap, the t ref, max parameter is met for all banks. during the t burst interval, the banks may be refreshed in a single burst, or they may be scattered throughout the interval. note that the first and last banks to be refreshed in the t burst interval are numbers 12 and 31, in order to match the example refresh sequence. data sheet e0251n20 (ver. 2.0) 53 pd488588ff-c80-40 figure 24-1 refa/refp refresh transaction example 9 x66t x66t ,0000 00066t e0000 00066t t , x le l y b lw e / lt l, w n ll ly l/ et e, ex ln el ey eb lx ee e/ wt lb ew en wl we w/ ,t ,, ww wn ,l ,y w, wx ,e ,/ wy wb ,w ,n 0t 0t 0u0 t0v077 l0v07 0u00 t0v070vv70 0t 9e i 0v0k00 0v0k00 0t 0u0 t0v07il7 0v0w66t 0v0x66t 0u00 t0v0709v7il7.l70 0l 0 0 figure 24-2 nap/pdn exit - t burst requirement 9 x66t x66t ,0000 00066t e0000 00066t t , x le l y b lw e / lt l, w n ll ly l/ et e, ex ln el ey eb lx ee e/ wt lb ew en wl we w/ ,t ,, ww wn ,l ,y w, wx ,e ,/ wy wb ,w ,n 0 0le0 0wl0 t l0000 t0000000l t9l t9l 000 0t00l , , 9 , , notes 1. use 0 for nap exit, 1 for pdn exit 2. device selection timing slot is selected by dqs field of napx register note 1 note 1 rop cop xop restricted dqs=0 dqs=1 note 2 note 2 stby scycle scycle (napx t )/(256 pdnx t ) 32 bank refresh sequence burst t data sheet e0251n20 (ver. 2.0) p 54 pd488588ff-c80-40 25. current and temperature control figure 25-1 shows an example of a transaction which performs current control calibration. it is necessary to perform this operation once to every rdram in every t cctrl interval in order to keep the i ol output current in its proper range. this example uses four colx packets with a cal command. these cause the rdram to drive four calibration packets q(a0) a time t cac later. an offset of t rdtocc must be placed between the q(a0) packet and read data q(a1) from the same device. these calibration packets are driven on the dqa4..3 and dqb4..3 wires. the tsq bit of the init register is driven on the dqa5 wire during same interval as the calibration packets. the remaining dqa and dqb wires are not used during these calibration packets. the last colx packet also contains a sam command (concatenated with the cal command). the rdram samples the last calibration packet and adjusts its i ol current value. unlike ref commands, cal and sam commands cannot be broadcast. this is because the calibration packets from different devices would interfere. therefore, a current control transaction must be sent every t cctrl /n, where n is the number of rdrams on the channel. the device field da of the address a0 in the cal/sam command should be incremented after each transaction. figure 25-2 shows an example of a temperature calibration sequence to the rdram. this sequence is broadcast once every t temp interval to all the rdrams on the channel. the tcen and tcal are rop commands, and cause the slew rate of the output drivers to adjust for temperature drift. during the quiet interval t tcquiet the devices being calibrated can ? t be read, but they can be written. figure 25-1 current control cal/sam transaction example ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 transaction a0: cal/sam a0 = {da, bx} t cctrl transaction a1: rd a1 = {da, bx} cal a0 cal a2 q (a0) t cac cal a0 cal a0 cal/sam a0 read data from a different device from an earlier rd command can be anywhere prior to the q(a0) packet. read data from a different device from a later rd command can be anywhere after to the q(a0) packet. read data from the same device from a later rd command must be at this packet position or later. read data from the same device from an earlier rd command must be at this packet position or earier. transaction a2: cal/sam a2 = {da, bx} dqa5 of the first calibrate packet has the inverted tsq bit of init control register; i.e. logic 0 or high voltage means hot temperature. when used for monitoring, it should be enabled with the dqa3 bit (current control one value) in case there is no rdram present: hottemp = /dqa5 ? note that dqb3 could be used instead of dqa3. t readtocc q (a1) q (a1) ccsamtoread t figure 25-2 temperature calibration (tcen-tcal) transactions to rdram ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 ca l tcen tcal tcen t tcal any row packet may be placed in the gap between the row packets with the tcen and tcal commands. no read data from devices being calibrated t temp t tcen t tcquiet data sheet e0251n20 (ver. 2.0) 55 pd488588ff-c80-40 26. electrical conditions 0 electrical conditions symbol parameter and conditions min. max. unit tj junction temperature under bias ? ? 0.13 2.50 + 0.13 v v dd , n ,v dda , n supply voltage droop (dc) during nap interval (t nlimt ) ? 2.0 % v dd , n ,v dda , n supply voltage ripple (ac) during nap interval (t nlimt ) ? 2.0 +2.0 % v cmos supply voltage for cmos pins (2.5v controllers) 2.50 ? 0.13 2.50 + 0.25 v supply voltage for cmos pins (1.8v controllers) 1.80 ? 0.1 1.80 + 0.2 v v term termination voltage 1.80 ? 0.1 1.80 + 0.1 v v ref reference voltage 1.40 ? 0.2 1.40 + 0.2 v v dil rsl data input - low voltage v ref ? 0.5 v ref ? 0.2 v v dih rsl data input - high voltage v ref + 0.2 v ref + 0.5 v v dis rsl data input swing : v dis = v dih ? v dil 0.4 1.0 v a di rsl data asymmetry : a di = [(v dih ? v ref ) + (v dil ? v ref )] / v dis 0 ? 20 % v x rsl clock input - crossing point of true and complement signals 1.3 1.8 v v cm rsl clock input - common mode v cm = (v cih + v cil ) / 2 1.4 1.7 v v cis, ctm rsl clock input swing : v cis = v cih ? v cil (ctm, ctmn pins). 0.35 1.00 v v cis, cfm rsl clock input swing : v cis = v cih ? v cil (cfm, cfmn pins). 0.225 1.00 v v il, cmos cmos input low voltage ? 0.3 + (v cmos / 2 ? 0.25) v v ih, cmos cmos input high voltage v cmos / 2+0.25 v cmos + 0.3 v data sheet e0251n20 (ver. 2.0) p 56 pd488588ff-c80-40 27. timing conditions timing conditions symbol parameter min. max. unit figures t cycle ctm and cfm cycle times -c80 2.50 3.83 ns figure 30-1 t cr , t cf ctm and cfm input rise and fall times 0.2 0.5 ns figure 30-1 t ch , t cl ctm and cfm high and low times 40% 60% t cycle figure 30-1 t tr ctm-cfm differential (mse/ms=0/0) 0.0 1.0 t cycle figure 22-1 (mse/ms=1/1) note1 0.9 1.0 figure 30-1 t dcw domain crossing window ? 0.1 +0.1 t cycle figure 35-1 t dr , t df dqa/dqb/row/col input rise/fall times 0.2 0.65 ns figure 31-1 t s , t h dqa/dqb/row/col-to-cfm t cycle =2.50ns 0.200 ? ns figure 31-1 setup/hold time t dr1 , t df1 sio0, sio1 input rise and fall times ? 5.0 ns figure 33-1 t dr2, t df2 cmd,sck input rise and fall times ? 2.0 ns figure 33-1 t cycle1 sck cycle time - serial control register transactions 1, 000 ? ns figure 33-1 sck cycle time - power transitions 10 ? ns figure 33-1 t ch1 , t cl1 sck high and low times 4.25 ? ns figure 33-1 t s1 cmd setup time to sck rising or falling edge note2 1.25 ? ns figure 33-1 t h1 cmd hold time to sck rising or falling edge note2 1 ? ns figure 33-1 t s2 sio0 setup time to sck falling edge 40 ? ns figure 33-1 t h2 sio0 hold time to sck falling edge 40 ? ns figure 33-1 t s3 pdev setup time on dqa5..0 to sck rising edge 0 ? ns figure 23-4, 33-2 t h3 pdev hold time on dqa5..0 to sck rising edge 5.5 ? ns figure 23-4, 33-2 t s4 row2..0, col4..0 setup time for quiet window note3 ? 1 ? t cycle figure 23-4 t h4 row2..0, col4..0 hold time for quiet window 5 ? t cycle figure 23-4 v il, cmos cmos input low voltage - over / undershoot voltage duration is less than or equal to 5 ns ? 0.7 +(v cmos /2 ? 0.6) v v ih, cmos cmos input high voltage - over / undershoot voltage duration is less than or equal to 5ns v cmos /2 + 0.6 v cmos + 0.7 v t npq quiet on row / col bits during nap / pdn entry 4 ? t cycle figure 23-3 t readtocc offset between read data and cc packets (same device) 12 ? t cycle figure 25-1 t ccsamtoread offset between cc packet and read data (same device) 8 ? t cycle figure 25-1 t ce ctm/cfm stable before nap/pdn exit 2 ? t cycle figure 23-4 t cd ctm/cfm stable after nap/pdn entry 100 ? t cycle figure 23-3 t frm row packet to col packet attn framing delay 7 ? t cycle figure 23-2 t nlimit maximum time in nap mode ? 10 s figure 23-1 t ref refresh interval ? 32 ms figure 24-1 t cctrl current control interval 34 t cycle 100 ms ? figure 25-1 t temp temperature control interval ? 100 ms figure 25-2 t tcen tce command to tcal command 150 ? t cycle figure 25-2 t tcal tcal command to quiet window 2 2 t cycle figure 25-2 t tcquiet quiet window (no read data) 140 ? t cycle figure 25-2 t pause rdram delay (no rsl operations allowed) ? 200 s figure 22-1 t burst interval after pdn or nap (with self-refresh) exit in which all banks of the rdram must be refreshed at least once. ? 200 s figure 24-2 data sheet e0251n20 (ver. 2.0) 57 pd488588ff-c80-40 notes 1. mse/ms are fields of the skip register. for this combination (skip override) the t dcw parameter range is effectively 0.0 to 0.0. 2. with v il,cmos = 0.5 v cmos ? 0.6 v and v ih,cmos = 0.5 v cmos + 0.6 v 3. effective hold becomes t h4 =t h4 + [pdnxa ? 64 ? t scycle + t pdnxb,max ] ? [pdnx ? 256 ? t scycle ] if [pdnx ? 256 ? t scycle ] < [pdnxa ? 64 ? t scycle + t pdnxb,max ]. see figure 23-4 . data sheet e0251n20 (ver. 2.0) p 58 pd488588ff-c80-40 28. electrical characteristics electrical characteristics symbol parameter and conditions min. max. unit ? 0.5 ? 10 +10 a i oh rsl output high current @ (0 ? 10 +10 a i all rsl i ol current @ v ol =0.9 v, v dd,min , t j,max note 30 90 ma ? ? 2.0 ma r out dynamic output impedance 150 ? ? ? 10.0 +10.0 a v ol,cmos cmos output low voltage @ i ol,cmos = 1.0 ma ? 0.3 v v oh,cmos cmos output high voltage @ i oh,cmos = ? 0.25 ma v cmos ? 0.3 ? v note this measurement is made in manual current control mode; i.e. with all output device legs sinking current. 29. timing characteristics timing characteristics symbol parameter min. max. unit figure(s) t q ctm-to-dqa/dqb output time t cycle = 2.50 ns ? 0.260 +0.260 ns figure 32-1 t qr , t qf dqa/dqb output rise and fall times 0.2 0.45 ns figure 32-1 t q1 sck-to-sio0 delay @ c load,max = 20 pf (sd read packet) ? 10 ns figure 34-1 t hr sck(pos)-to-sio0 delay @ c load,max = 20pf (sd read data hold) 2 ? ns figure 34-1 t qr1 , t qf1 sio out rise/fall @ c load,max = 20 pf ? 5 ns figure 34-1 t prop1 sio0-to-sio1 or sio1-to-sio0 delay @ c load,max = 20 pf ? 10 ns figure 34-1 t napxa nap exit delay - phase a ? 50 ns figure 23-4 t napxb nap exit delay - phase b ? 40 ns figure 23-4 t pdnxa pdn exit delay - phase a ? 4 ? 9,000 t cycle figure 23-4 t as attn-to-stby power state delay ? 1 t cycle figure 23-2 t sa stby-to-attn power state delay ? 0 t cycle figure 23-2 t asn attn/stby-to-nap power state delay ? 8 t cycle figure 23-3 t asp attn/stby-to-pdn power state delay ? 8 t cycle figure 23-3 data sheet e0251n20 (ver. 2.0) 59 pd488588ff-c80-40 30. rsl clocking figure 30-1 is a timing diagram which shows the detailed requirements for the rsl clock signals on the channel. the ctm and ctmn are differential clock inputs used for transmitting information on the dqa and dqb, outputs. most timing is measured relative to the points where they cross. the t cycle parameter is measured from the falling ctm edge to the falling ctm edge. the t cl and t ch parameters are measured from falling to rising and rising to falling edges of ctm. the t cr and t cf rise-and fall-time parameters are measured at the 20 % and 80 % points. the cfm and cfmn are differential clock outputs used for receiving information on the dqa, dqb, row and col outputs. most timing is measured relative to the points where they cross. the t cycle parameter is measured from the falling cfm edge to the falling cfm edge. the t cl and t ch parameters are measured from falling to rising and rising to falling edges of cfm. the t cr and t cf rise- and fall-time parameters are measured at the 20 % and 80 % points. the t tr parameters specifies the phase difference that may be tolerated with respect to the ctm and cfm differential clock inputs (the ctm pair is always earlier). figure 30-1 rsl timing - clock signals v cih 80% 50% 20% v cil ctm ctmn t cl t ch t cycle t cr t cf t cr t cf v cih 80% 50% 20% v cil cfm cfmn t cr t cf t cr t cf t cl t ch t cycle t tr v x- v x- v x+ v x+ v cm v cm data sheet e0251n20 (ver. 2.0) p 60 pd488588ff-c80-40 31. rsl - receive timing figure 31-1 is a timing diagram which shows the detailed requirements for the rsl input signals on the channel. the dqa, dqb, row, and col signals are inputs which receive information transmitted by a direct rac on the channel. each signal is sampled twice per t cycle interval. the set/hold window of the sample points is t s /t h . the sample points are centered at the 0 % and 50 % points of a cycle, measured relative to the crossing points of the falling cfm clock edge. the set and hold parameters are measured at the v ref voltage point of the input transition. the t dr and t df rise- and fall-time parameters are measured at the 20 % and 80 % points of the input transition. figure 31-1 rsl timing - data signals for receive v cih 80% 50% 20% v cil cfm cfmn even t h odd cycle v dih 80% 20% v dil dqa dqb t dr t df t s t h t s 0.5 t v ref row col v x- v x+ v cm data sheet e0251n20 (ver. 2.0) 61 pd488588ff-c80-40 32. rsl - transmit timing figure 32-1 is a timing diagram which shows the detailed requirements for the rsl output signals on the channel. the dqa and dqb signals are outputs to transmit information that is received by a direct rac on the channel. each signal is driven twice per t cycle interval. the beginning and end of the even transmit window is at the 75 % point of the previous cycle and at the 25 % point of the current cycle. the beginning and end of the odd transmit window is at the 25 % point and at the 75 % point of the current cycle. these transmit points are measured relative to the crossing points of the falling ctm clock edge. the size of the actual transmit window is less than the ideal t cycle /2, as indicated by the non-zero valued of t q,min and t q,max . the t q parameters are measured at the 50 % voltage point of the output transition. the t qr and t qf rise- and fall-time parameters are measured at the 20 % and 80 % points of the output transition. figure 32-1 rsl timing - data signals for transmit v cih 80% 50% 20% v cil ctm ctmn even t q,min odd cycle v qh 80% 20% v ql dqa dqb t qr t qf t q,max t q,min t q,max 0.25 t 50% cycle 0.75 t cycle 0.75 t v x- v x+ v cm data sheet e0251n20 (ver. 2.0) p 62 pd488588ff-c80-40 33. cmos - receive timing figure 33-1 is a timing diagram which shows the detailed requirements for the cmos input signals. the cmd and sio0 signals are inputs which receive information transmitted by a controller (or by another rdram ? s sio1 output). sck is the cmos clock signal driven by the controller. all signals are high true. the cycle time, high phase time, and low phase time of the sck clock are t cycle1 , t ch1 and t cl1 , all measured at the 50 % level. the rise and fall times of sck, cmd, and sio0 are t dr1 and t df1 , measured at the 20 % and 80 % levels. the cmd signal is sampled twice per t cycle1 interval, on the rising edge (odd data) and the falling edge (even data). the set/hold window of the sample points is t s1 /t h1 . the sck and cmd timing points are measured at the 50 % level. the sio0 signal is sampled once per t cycle1 interval on the falling edge. the set/hold window of the sample points is t s2 /t h2 . the sck and sio0 timing points are measured at the 50 % level. figure 33-1 cmos timing - data signals for receive xawy data sheet e0251n20 (ver. 2.0) 63 pd488588ff-c80-40 the sck clock is also used for sampling data on rsl input in one situation. figure23-4 shows the pdn and nap exit sequences. if the psx field of the init register is one (figure 22-1 control registers (1/7) ? init register ? ), then the pdn and nap exit sequences are broadcast; i.e. all rdrams that are in pdn or nap will perform the exit sequence. if the psx field of the init register is zero, then the pdn and nap exit sequences are directed; i.e. only one rdram that is in pdn or nap will perform the exit sequence. the address of that rdram is specified on the dqa[5:0] bus in the set hold window t s3 /t h3 around the rising edge of sck. this is shown figure 33-2. the sck timing point is measured at the 50 % level, and the dqa [5:0] bus signals are measured at the v ref level. figure 33-2 cmos timing - device address for nap or pdn exit v ih,cmos 80% 50% 20% v il,cmos sck pdev v dih 80% 20% v dil dqa[5:0] v t s3 t h3 ref |
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